Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors

A CNN-based algorithm, adequate for short exposure image processing and an application-specific computing architecture developed to accelerate its execution are presented. Algorithm is based on a flexible and scalable CNN architecture specifically designed to optimize the projection of CNN kernels on a programmable circuit. The objective of the proposed algorithm is to minimize the adverse effect that atmospheric disturbance has on the images obtained by terrestrial telescopes. Algorithm main features are that it can be adapted to the detection of several astronomical objects and it supports multi-stellar images. The implementation platform made use of a High Performance Reconfigurable Computer (HPRC) combining general purpose standard microprocessors with custom hardware accelerators based on FPGAs, to speed up execution time. The hardware synthesis of the CNN model has been carried out using high level hardware description languages, instead of traditional Hardware Description Languages (HDL).

A mechanism is presented to represent failures in complex combinational digital and VLSI designs at a high level, referred to as behavior fault models. The advantages of behavior fault modeling include early estimates of reliability of the design in the design process, reduced CPU time for fault simulation, and results that may be more comprehensive to the high-level architects. Digital and VLSI components are expressed in a high-level hardware description language and the fault models proposed are based on the failure modes of the language constructs of a generic hardware-description language. Evaluation of such fault models is also reported through a correlation of the behavior fault simulation results of representative example designs with fault simulation of equivalent gate-level representations in the presence of stuck-at faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Self-healing reconfigurable logic using autonomous group testing

Static worst-case timing analysis is important in the context of safety-critical systems as it is one approach that could be used to validate the required timing bounds. In order to derive accurate bounds, the worst-case timing analysis is performed under (micro)-architecture consideration, consequently, these bounds are expressed in processor cycles. The required (micro)-architecture models are usually constructed by hand, from processor manuals and validated through testing. Recent advances in hardware design promote open hardware initiatives and high-level Hardware Description Languages (HDLs), revisiting the perspectives to automatically construct (micro)-architecture models for worst-case timing analysis. In this paper, we present an approach concerning the construction of pipeline datapath models from processor designs described in high-level HDLs. We propose a methodology based on the Chisel/FIRRTL Hardware Compiler Framework which we apply on several open-source RISC-V processors.

Mission-critical systems require increasing capability for fault handling and self-adaptation as their system complexities and inter-dependencies increase. Organic Computing (OC) architectures utilize biologically-inspired self-x properties which include self-configuration, self-reorganization, and self-healing which comprise the focus of this paper. To provide OC architectures with sufficient capability for exhibiting self-adaptive behavior, reconfigurable logic devices offer a suitable hardware platform. SRAM-based Field Programmable Gate Array (FPGA) logic devices can realize self-adaptation within their reconfigurable logic fabric using Evolvable Hardware techniques based on crossover, mutation, and iterative selection with intrinsic fitness assessment of the underlying hardware resources. In this paper, a dual-layer Organic Computing architecture called the Organic Embedded System (OES) is prototyped on a Xilinx FPGA reconfigurable fabric and assessed for maintainability metrics of completeness of repair, repair time, and degraded throughput during the repair phase. The approach used extends a widely known generic OC platform consisting of two layers: the Functional Layer and the Autonomic Layer. The Autonomic layer contains Autonomic Elements (AEs) that are responsible for correct operation of the corresponding Functional Elements (FEs) present on the Functional Layer. Innovations include autonomously degraded online throughput during regeneration, spare configuration aging and outlier driven repair assessment, and a uniform design for AEs despite the fact that they monitor different types of FEs. Using the OES approach; a malfunctioning or faulty AE among the population can be distinguished by its discrepant performance. The OES approach is implemented using high-level Hardware Description Language (HDL) which directs a Supervisor Element (SE) to function as a fault management unit through the collection of AE information. Experimental results show that the OES Autonomic Layer demonstrates 100% faulty component isolation for both FEs and AEs with randomly injected single faults. Using logic circuits from the MCNC-91 benchmark test set, throughput during repair phases averaged 75.05%, 82.21%, and 65.21% for the z4ml (2-bit adder), cm85a (high fan-in combinational logic), and cm138a (balanced I/O combinational logic) circuits respectively under stated conditions.

There is a very strong requirement for high level mixed-signal simulation in the design of complex mixed-signal ASICs, for design verification, design analysis and system level modelling. The key issues in such simulations are high level analogue modelling, and compatibility between analogue and digital simulation. The two main alternative approaches are to link together a circuit simulator and a logic simulator, providing some method of high level analogue modelling in the circuit simulator, or to develop high level event-driven models of analogue functions in the context of a digital simulator. There are advantages and disadvantages to each approach.

We describe a practical method of generating production ready timing violation resilient asynchronous circuits with conditional communication from a high level hardware description language. Designs written in SystemVerilogCSP are taped out on a 3.3 million transistor chip. We present two slackless scan-enabled asynchronous controllers based on the Click template that saved an average area of 14% in our application.

Arithmetic and Logic Unit (ALU) is the most crucial and core component of central processing unit as well as of number of embedded systems and microprocessors. ALU consists of many computational units like adders, multipliers, logical units etc. Vedic Mathematics concepts are proposed here for designing the computational units of an 8-bit ALU. Here, a high-speed 8×8 bit multiplier is proposed which is based on the Vedic multiplier mechanism. A divider based on vedic mathematics is also proposed here. The proposed Vedic mathematics based ALU is designed using high level hardware description language – Verilog, followed by synthesization using EDA tool, Xilinx ISE 14.1. Finally, the synthesized circuit has been implemented on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) device.

In this dissertation we develop numerical algorithms and software tools to facilitate parallel solutions of nonlinear programming (NLP) problems. In particular, we address large-scale, block-structured problems with an intrinsic decomposable configuration. These problems arise in a great number of engineering applications, including parameter estimation, optimal control, network optimization, and stochastic programming. The structure of these problems can be leveraged by optimization solvers to accelerate solutions and overcome memory limitations, and we propose variants to two classes of optimization algorithms: augmented Lagrangian (AL) schemes and Schur-complement interior-point methods. The convergence properties of augmented Lagrangian decomposition schemes like the alternating direction method of multipliers (ADMM) and progressive hedging (PH) are well established for convex optimization but convergence guarantees in non-convex settings are still poorly understood. In practice, however, ADMM and PH often perform satisfactorily in complex non-convex NLPs. In this work, we study connections between the method of multipliers (MM), ADMM, and PH to derive benchmarking metrics that explain why PH and ADMM work in practice. We illustrate the concepts using challenging dynamic optimization problems. Our exposition seeks to establish more formalism in benchmarking ADMM, PH, and AL schemes and to motivate algorithmic improvements. The effectiveness of nonlinear interior-point solvers for solving large-scale problems relies quite heavily on the solution of the underlying linear algebra systems. The schur-complement decomposition is very effective for parallelizing the solution of linear systems with modest coupling. However, for systems with large number of coupling variables the schur-complement method does not scale favorably. We implement an approach that uses a Krylov solver (GMRES) preconditioned with ADMM to solve block-structured linear systems that arise in the interior-point method. We show that this ADMM-GMRES approach overcomes the well-known scalability issues of Schur decomposition. One important drawback of using decomposition approaches like ADMM and PH is their convergence rate. Unlike Schur-complement interior-point algorithms that have super-linear convergence, augmented Lagrangian approaches typically exhibit linear and sublinear rates. We exploit connections between ADMM and the Schur-complement decomposition to derive an accelerated version of ADMM. Specifically, we study the effectiveness of performing a Newton-Raphson algorithm to compute multiplier estimates for augmented Lagrangian methods. We demonstrate using two-stage stochastic programming problems that our multiplier update achieves convergence in fewer iterations for MM on general nonlinear problems. In the case of ADMM, the newton update significantly reduces the number of subproblem solves for convex quadratic programs (QPs). Moreover, we show that using newton multiplier updates makes the method robust to the selection of the penalty parameter. Traditionally, state-of-the-art optimization solvers are implemented in low-level programming languages. In our experience, the development of decomposition algorithms in these frameworks is challenging. They present a steep learning curve and can slow the development and testing of new numerical algorithms. To mitigate these challenges, we developed PyNumero, a new open source framework implemented in Python and C++. The package seeks to facilitate development of optimization algorithms for large-scale optimization within a high-level programming environment while at the same time minimizing the computational burden of using Python. The efficiency of PyNumero is illustrated by implementing algorithms for problems arising in stochastic programming and optimal control. Timing results are presented for both serial and parallel implementations. Our computational studies demonstrate that with the appropriate balance between compiled code and Python, efficient implementations of optimization algorithms are achievable in these high-level languages.

Recent advances in programming languages have sometimes drastically altered program structure as in the Reduction Languages of Backus (3) or produced less drastic but nonetheless dramatic effects like the elimination of the “goto” statement in an increasing number of “structured” programming languages (4). Now waiting in the wings are demands for topologically simpler program structures which will ease code optimization problems, increase programmer productivity, and aid automatic verification of program correctness. In these respects, perhaps the most advanced high-level programming language yet developed is Aiken Dynamic Algebra (ADA), the younger sister of APL (5, 6, 7). Boyce (8) has already shown the improved efficiency of ADA on pipeline and parallel machines, but his results for ADA in a sequential environment were inconclusive. This study reports the comparison of a sequential ADA implementation with the standard instruction sets of two existing sequential machine designs, the IBM 1130 and the IBM 360. Addition of 150 microinstructions allowed simultaneously a 5 to 35% decrease in execution time and a 5 to 40% decrease in the storage requirements for code to implement identical algorithms.

Recent advances in programming languages have sometimes drastically altered program structure as in the Reduction Languages of Backus (3) or produced less drastic but nonetheless dramatic effects like the elimination of the “goto” statement in an increasing number of “structured” programming languages (4). Now waiting in the wings are demands for topologically simpler program structures which will ease code optimization problems, increase programmer productivity, and aid automatic verification of program correctness. In these respects, perhaps the most advanced high-level programming language yet developed is Aiken Dynamic Algebra (ADA), the younger sister of APL (5, 6, 7). Boyce (8) has already shown the improved efficiency of ADA on pipeline and parallel machines, but his results for ADA in a sequential environment were inconclusive. This study reports the comparison of a sequential ADA implementation with the standard instruction sets of two existing sequential machine designs, the IBM 1130 and the IBM 360. Addition of 150 microinstructions allowed simultaneously a 5 to 35% decrease in execution time and a 5 to 40% decrease in the storage requirements for code to implement identical algorithms.

A number of recent articles have focused on the design of high speed discrete-event simulation (DES) machines for digital logic simulation. These investigations are in response to the enormous costs associated with the simulation of complex (VLSI) digital circuits for logic verification and fault analysis. One approach to reducing simulation costs is to design special purpose digital computers that are tailored to the logic simulation test. This paper is concerned with the architecture of such logic machines. The paper has three principal parts. First, a taxonomy of logic machine architectures is presented. The taxonomy focuses on the central components of the logic simulation algorithms and on architectural alternatives for increasing the speed of the simulation process. It thus represents a basis for discussing and differentiating between proposed architectures and also results in the identification of several new architectures. Although developed for digital logic simulators., the taxonomy can be used for general DES machines. Second, a performance measure is presented which permits evaluation of DES machines. Finally several DES machine designs are described and categorized using the taxonomy.

Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs

Steps towards the implementation of a parallel code executor

General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. This paper addresses logic simulation on parallel machines by exploiting the concurrency in the circuit being simulated (called data parallelism) as opposed to exploiting parallelism inherent in the simulation algorithm itself (called functional parallelism). The most crucial step in obtaining the maximum parallelism using data parallelism is the partitioning of circuit elements. We introduce a cost function which tries to model the simulation of a logic circuit in a parallel environment. The cost function tries to estimate the parallel run time for logic simulation given the processor assignment and the underlying multiprocessor architecture. We then present different heuristic algorithms to partition the circuit and evaluate the efficiency of these algorithms using the proposed cost function. Partitioning algorithms for both event-driven and compiled code simulation are given.