Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs

Enabling fail-operational behavior of safety-critical software is essential to achieve autonomous driving. At the same time, automotive vendors have to regularly deliver over-the-air software updates. Here, the challenge is to enable a flexible and dynamic system behavior while offering, at the same time, a predictable and deterministic behavior of time-critical software. Thus, it is necessary to verify that timing constraints can be met even during failover scenarios. For this purpose, we present a formal analysis to derive the worst-case application failover time. Without such an automated worst-case failover timing analysis, it would not be possible to enable a dynamic behavior of safety-critical software within safe bounds. We support our formal analysis by conducting experiments on a hardware platform using a distributed fail-operational neural network. Our randomly generated worst-case results are as close as 6.0% below our analytically derived exact bound. Overall, our presented worst-case failover timing analysis allows to conduct an automated analysis at run-time to verify that the system operates within the bounds of the over timing constraint such that a dynamic and safe behavior of autonomous systems can be ensured.

Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone.

In this paper, a triple-mode MAP/VA IP for advanced wireless communication Systems is implemented in 0.18mum CMOS process. We employ triple-mode MAP/VA timing charts that can run two different algorithms at the same time by complementing the idle time of each other. In order to conform to the advance communication standard, our IP can also perform as a reconfigurable trellis decoder. For WCDMA standard, this IP can operate at clock frequency of 100 MHz and achieve throughput rate of 4.17Mbps@6 iterations for turbo decoding and 1.56Mbps for convolutional decoding in concurrent MAP/VA mode from the worst-case static timing analysis and post-layout simulation

Circuit analysis with respect to aging-induced degradation is critical to ensure correct operation throughout the entire lifetime of a chip. However, state-of-the-art techniques only allow for the consideration of uniformly applied degradation, despite the fact that different workloads will lead to different degradations due to the different induced activities. This imposes over-pessimism in estimating the required timing guardbands, resulting in unnecessary losses of performance and efficiency. In this work, we propose an approach that takes real-world workload dependencies into account and generates workload-specific aging-aware standard cell libraries. This allows for accurate analysis of circuits under the actual effect of aging-induced degradation. We make use of machine learning techniques to overcome infeasible simulation times for individual transistor aging while sustaining high accuracy. In our evaluation on the PULP microprocessor, we achieve predictions of workload-dependent aging-aware standard cells with an average accuracy (R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> score) of 94.7 %. Using the predicted cell libraries in Static Timing Analysis, timing guardbands are reported with an error of less than 0.1 %. We demonstrate that timing guardband requirements can be reduced by up to 21 % by considering specific workloads over worst-case analysis as performed in state-of-the-art tool flows.

With the rapid development of parallel programming techniques and the widespread use of multiprocessors, scheduling and analysis techniques supporting parallel real-time tasks become a critical topic for multiprocessor real-time systems. Global scheduling that allows the vertices of a parallel task to execute on any processor is a promising scheduling approach with guaranteed theoretical bounds and wide use in practice. However, the complex internal structure of parallel tasks leads to extensive inner- and inter-task interference, which leads to significant pessimism in the worst-case timing analysis. In this paper, a global fixed-priority (G-FP) scheduling with constrained parallelism for parallel real-time tasks based on the sporadic directed acyclic graph (DAG) model is proposed. Each DAG task is assigned a parallel threshold, such that the number of processors occupied by the task is limited to the parallel threshold of the task at a time. We propose a heuristic algorithm to set the parallel threshold and present a response-time analysis (RTA) to exploit the feature of the constrained parallel scheduling. Experiments with randomly generated tasks show that the proposed approach improves the schedulability upon G-FP and federated scheduling in terms of acceptance ratio.

Self-healing reconfigurable logic using autonomous group testing

A mechanism is presented to represent failures in complex combinational digital and VLSI designs at a high level, referred to as behavior fault models. The advantages of behavior fault modeling include early estimates of reliability of the design in the design process, reduced CPU time for fault simulation, and results that may be more comprehensive to the high-level architects. Digital and VLSI components are expressed in a high-level hardware description language and the fault models proposed are based on the failure modes of the language constructs of a generic hardware-description language. Evaluation of such fault models is also reported through a correlation of the behavior fault simulation results of representative example designs with fault simulation of equivalent gate-level representations in the presence of stuck-at faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in distributed conservative digital circuit simulation algorithms in that it permits the use of any number of non-zero propagation delays for every path between the input and output of every hardware entity. P/sup 2/EDAS permits, accurate, concurrent, asynchronous, and efficient, i.e. deadlock free and null-message free, execution of sequential and combinatorial digital designs on parallel processors. It is a conservative algorithm in that only those output transitions, if any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, preemption of inconsistent events are allowed. P/sup 2/EDAS extends to any simulator based on high-level hardware description language. This paper presents a detailed description of the algorithm.

Mission-critical systems require increasing capability for fault handling and self-adaptation as their system complexities and inter-dependencies increase. Organic Computing (OC) architectures utilize biologically-inspired self-x properties which include self-configuration, self-reorganization, and self-healing which comprise the focus of this paper. To provide OC architectures with sufficient capability for exhibiting self-adaptive behavior, reconfigurable logic devices offer a suitable hardware platform. SRAM-based Field Programmable Gate Array (FPGA) logic devices can realize self-adaptation within their reconfigurable logic fabric using Evolvable Hardware techniques based on crossover, mutation, and iterative selection with intrinsic fitness assessment of the underlying hardware resources. In this paper, a dual-layer Organic Computing architecture called the Organic Embedded System (OES) is prototyped on a Xilinx FPGA reconfigurable fabric and assessed for maintainability metrics of completeness of repair, repair time, and degraded throughput during the repair phase. The approach used extends a widely known generic OC platform consisting of two layers: the Functional Layer and the Autonomic Layer. The Autonomic layer contains Autonomic Elements (AEs) that are responsible for correct operation of the corresponding Functional Elements (FEs) present on the Functional Layer. Innovations include autonomously degraded online throughput during regeneration, spare configuration aging and outlier driven repair assessment, and a uniform design for AEs despite the fact that they monitor different types of FEs. Using the OES approach; a malfunctioning or faulty AE among the population can be distinguished by its discrepant performance. The OES approach is implemented using high-level Hardware Description Language (HDL) which directs a Supervisor Element (SE) to function as a fault management unit through the collection of AE information. Experimental results show that the OES Autonomic Layer demonstrates 100% faulty component isolation for both FEs and AEs with randomly injected single faults. Using logic circuits from the MCNC-91 benchmark test set, throughput during repair phases averaged 75.05%, 82.21%, and 65.21% for the z4ml (2-bit adder), cm85a (high fan-in combinational logic), and cm138a (balanced I/O combinational logic) circuits respectively under stated conditions.

Buffer allocation for real-time streaming applications, modeled as dataflow graphs, minimizes the total memory consumption while reserving sufficient space for each data production without overwriting any live data and guaranteeing the satisfaction of real-time constraints. We focus on the problem of buffer allocation for systems without back-pressure. Since systems without back-pressure lack blocking behavior at the side of the producer, buffer allocation requires both best- and worst-case timing analysis. Moreover, the dynamic (data-dependent) behavior in these applications makes buffer allocation challenging from the best- and worst-case- timing analysis perspective. We argue that static dataflow cannot conveniently express the dynamic behavior of these applications, leading to overallocation of memory resources. Mode-controlled Dataflow (MCDF) is a restricted form of dynamic dataflow that allows mode switching at runtime and static analysis of real-time constraints. In this paper, we address the problem of buffer allocation for MCDF graphs scheduled on systems without back-pressure. We consider practically relevant applications that can be modeled in MCDF using recurrent-choice mode sequence that consists of the mode sequences of equal length; it provides tractable analysis. Our contribution is a buffer allocation algorithm that achieves up to 36% reduction in total memory consumption compared to the current state-of-the-art for an LTE and an LTE Advanced receiver use cases.

As design size gets larger and becomes more complicated with feature integration, the runtime for Static Timing Analysis (STA) becomes more of a concern. Due to time-to-market pressure, the validation of the design is performed in parallel with the physical synthesis flow; therefore it is not uncommon to find last minute critical logic bugs during final design integration iterations. However, timing verification needs to be run on full-chip level to ensure that the check is comprehensive. This paper proposes a method to isolate only those logics which are affected by the Engineering Change Order (ECO) for STA. This simplification will allow faster ECO iteration to enable a more efficient timing convergence. The proposed method is also suitable to be used for multithreading in STA engines to speed-up timing verification due to ECO changes. Engineering Change Order (ECO), Static Timing Analysis (STA), Incremental Static Timing Analysis, VLSI design

Static timing analysis techniques are widely used to verify the timing behavior of large digital designs implemented predominantly in conventional static CMOS. These techniques, however, are not sufficient to completely verify the dynamic circuit families now finding favor in high-performance designs. In this paper, we describe an approach that extends static timing analysis to a high-performance dynamic CMOS logic family called self-resetting CMOS (SRCMOS). Due to the circuit structure employed in SRCMOS, designs naturally decompose into a hierarchy of gates and macros; timing analysis must address and preferably exploit this hierarchy. At the gate level, three categories of constraints on pulse timing arise from considering the effects of pulse width, overlap, and collisions. Timing analysis is performed at the macro level, by a) performing timing tests at macro boundaries and b) using macro-level delay models. We define various macro-level timing tests which ensure that fundamental gate-level timing constraints are satisfied. We extend the standard delay model to handle leading and trailing edges of signal pulses, across-chip variations, trading of signals, and slow and fast operating conditions. We have developed an SRCMOS timing analyzer based on this approach; the analyzer implemented as extensions to a standard static timing analysis program, thus facilitating its integration into an existing design system and methodology.

Static timing analysis (STA) is an essential yet time-consuming task during the circuit design flow to ensure the correctness and performance of the design. Thanks to the advancement of general-purpose computing on graphics processing units (GPUs), new possibilities and challenges have arisen for boosting the performance of STA. In this work, we present an efficient and holistic GPU-accelerated STA engine. We accelerate major STA tasks, including levelization, delay computation, graph propagation, and multicorner analysis, by developing high-performance GPU kernels and data structures. By dividing the STA workloads into CPU–GPU concurrent tasks with managed dependencies, our acceleration framework supports versatile incremental updates. Furthermore, we have extended our approach to multicorner analysis by exploring a large amount of corner-level data parallelism using GPU computing. Our implementation based on the open-source STA engine OpenTimer has achieved up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.07\times $ </tex-math></inline-formula> speed-up on single corner analysis, and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25.67\times $ </tex-math></inline-formula> speed-up on multicorner analysis on TAU 2015 contest designs and a 14-nm technology.

Recent static timing analysis (STA) tools have utilized task dependency graph (TDG) parallelism to enhance the STA runtime performance. Although TDG parallelism shows promising speedup, the overhead of scheduling a TDG can become dominant as the TDG becomes larger. To minimize the scheduling overhead, several TDG partitioning algorithms have been proposed to reduce the TDG size without affecting its task parallelism. Despite improved performance, existing TDG partitioners all fall short of incremental partitioning, limiting their practical use in STA tools that support timing-driven operations. To overcome this limitation, we propose iTAP, an incremental TDG partitioner to fully leverage the power of TDG partitioning in task-parallel STA applications. Compared to a state-of-the-art full TDG partitioner, iTAP enhances the overall STA performance by up to 2.97×.