Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs

Model checking by symbolic trajectory evaluation, orchestrated in a flexible functional-programming framework, is a well-established technology for correctness verification of industrial-scale circuit designs. Most verifications in this domain require decomposition into subproblems that symbolic trajectory evaluation can handle, and deductive theorem proving has long been proposed as a complement to symbolic trajectory evaluation to enable such compositional reasoning. This paper describes an approach to verification by symbolic simulation, called Relational STE, that raises verification properties to the purely logical level suitable for compositional reasoning in a theorem prover. We also introduce a new deductive theorem prover, called Goaled, that has been integrated into Intel's Forte verification framework for this purpose. We illustrate the effectiveness of this combination of technologies by describing a general framework, accessible to non-experts, that is widely used for verification and regression validation of integer multipliers at Intel.

Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practical asynchronous circuit and system design in four areas: controllers, datapaths, processors, and the design of asynchronous/synchronous interfaces.

Two recent developments in asynchronous circuit design are explored by means of a case study (polynomial division) in digital signal processing. The first development is a new formal method, the handshake algebra of M.B. Josephs, J.T. Udding and J.T. Yantchev (1993), that is suitable for specifying, deriving, and verifying circuits that follow a handshaking protocol. The second development is an architecture, counterflow pipelines, that R.F. Sproull (1994) has recently suggested, which is attractive to implement asynchronously.

Asynchronous circuit design has been a topic of study for over 40 years. Only recently has this study turned to the practical issues of building useful CAD tool support that approaches the level of functionality available in synchronous VLSI CAD systems. The existence of these asynchronous CAD systems enables today’s designers to construct asynchronous VLSI devices of significant size and scope. This chapter provides a reasonably detailed description of the process of developing a set of VLSI CAD tools which permit correct controller circuits to be synthesized from finite state machine style specifications. The tools were developed in two stages. The first stage resulted in a set of tools called MEAT, which were used to implement a 300,000 transistor multiprocessor routing chip called the Post Office. This Post Office experience provided the motivation for the second stage which resulted in the STETSON tool set which is integrated with the Mentor VLSI tool suite and was used to synthesize a low-power infrared transceiver chip called ABCS. The chapter presents a somewhat chronological view of the development of the CAD methods and provides examples of how well these methods worked in a practical design setting.KeywordsState MachineFlow TableDesign StyleLogic HazardAsynchronous CircuitThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Alain Martin has developed a design method for asynchronous circuits whereby a specification is refined through a series of distinct stages to a gate implementation. The Circal system is able to check equivalence between terms of the Circal process algebra. The system can be used to verify the results of some of Martin's refinements and the gate implementations. It can also be used to analyse the operator network for the necessity of isochronic forks.

In this paper, the authors present a rapid prototyping environment for teaching digital logic design. Their primary goal was to build an FPGA based hardware prototyping system that provides sufficient flexibility for the implementation and functional verification of various digital circuit designs. Since the system is intended to be used as an experimental and demonstration board to support digital design courses and practices for the undergraduate students, it is simple to use and completely supported by the software for automatic implementation of digital circuits. The prototyping environment consists of a PC and the programmable board composed of 3 FPGAs. One FPGA is used to implement the digital circuit, while the rest of the devices implement an interface between the digital circuit and the PC. The PC is used for designing a digital circuit, automatic generation of the interface logic, programming the FPGAs and as a test engine for functional verification of the designed circuit. The presented environment is used in the regular educational process and the sample student projects are summarized.

This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in distributed conservative digital circuit simulation algorithms in that it permits the use of any number of non-zero propagation delays for every path between the input and output of every hardware entity. P/sup 2/EDAS permits, accurate, concurrent, asynchronous, and efficient, i.e. deadlock free and null-message free, execution of sequential and combinatorial digital designs on parallel processors. It is a conservative algorithm in that only those output transitions, if any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, preemption of inconsistent events are allowed. P/sup 2/EDAS extends to any simulator based on high-level hardware description language. This paper presents a detailed description of the algorithm.

Steps towards the implementation of a parallel code executor

Synchronous digital systems have been presenting serious problems of implementation in DSM (deep sub-micron) VLSI technology, for which the asynchronous paradigm has become an interesting alternative. Unfortunately, the topic of synthesis of asynchronous digital systems has been ignored or presents only a few numbers of teaching classes in most courses in electrical engineering, due the difficulty of different styles of asynchronous design, what requires many hours of classroom teaching. In this paper we propose a methodology for synthesis of asynchronous systems that requires just few hours of classroom teaching, being interesting to be incorporated in the subject of logic design. Starting from the RTL (Register Transfer Level) description of synchronous systems, the proposed method synthesizes the asynchronous system in the “decomposition” style, which is defined by XBM_AFSM (extended burst-mode asynchronous finite state machine) + datapath synchronous. A simple procedure is used to convert the specification of SFSM to the XBM specification, which describes the XBM_AFSM. Through a case study, it is shown the simplicity of the methodology, resulting in high-performance circuits.

In this chapter we outline a process algebra, whose name — Petri Box Calculus (PBC) — arises from its original Petri net semantics [6, 7]. PBC combines a number of features taken from other process algebras, such as COSY (Concurrent Systems notation, [62]), CCS (Calculus of Communicating Systems, [80, 81]), SCCS (Synchronous CCS, [81]), CSP (Communicating Sequential Processes, [58]), TCSP (Theoretical CSP, [59]) and ACP (Algebra of Communicating Processes, [2]). However, there are some fundamental differences with each of these process algebras since PBC has been designed with two specific objectives in mind: To support a compositional Petri net semantics, together with an equivalent — more syntax-oriented — structured operational semantics (SOS) [89]. To provide as flexible as possible a basis for developing a compositional semantics of high-level concurrent specification and programming languages with full data and control features.

A computer controlled test system has been developed for VLSI/LSI circuit failure analysis and design verification using the electron beam of the SEM (Scanning Electron Microscope) as a non-contacting probe. This system inputs truth tables to device under test, determines, stores, and verifies the logic state of internal nodes under computer controL Practical applications of the system to design verification are described. The system concept has been demonstrated using the standard equipment with minor additions.

The operation of a design automation system for custom integrated circuits is described. The procedures are based upon standard cell libraries and a sophisticated automatic placement and routing program. The economic viability of automated layout techniques has been demonstrated by circuit layout, design verification and system integration of twenty five custom PMOS/LSI devices in 1975.

This paper addresses the problem of scheduling n jobs on a single machine and on m identical parallel machines to minimize the completion time variance of jobs. This problem of scheduling jobs on parallel machines is motivated by a case study in an automobile ancillary unit. First, a heuristic to solve the single-machine scheduling problem is proposed. The parallel-machine scheduling problem is solved in two phases: job-allocation phase and job-sequencing phase. Two heuristics are proposed in the job-allocation phase, whereas in the job-scheduling phase, the single-machine scheduling approach is used. In this paper, both versions of parallel-machine scheduling problem (restricted and unrestricted) are considered. A good upper bound is obtained using a genetic algorithm, to evaluate the performance of the proposed heuristics for the parallel-machine scheduling problem. An extensive computation evaluation of the proposed heuristics is presented for both single-machine scheduling problem and the parallel-machine scheduling problem (especially considering the case study), along with the comparison of performances with the existing heuristics in the literature.

Asynchronous systems are designed without any global clock signal. Here computation is achieved by a series of events represented by signal transition edges; hence the speed of computation is determined by the signal propagation delay of the asynchronous circuit and not on the global clock. Some notable problems in synchronous circuit design due to higher performance demand are clock skew, power dissipation and worst case performance. The asynchronous circuit design which generally does not suffer from these problems, is experiencing a significant resurgence of interest and research activity. In this work, we propose analysis and design of reversible Hazard free latches for the first time in Reversible literature. Two methods are proposed for static hazard removal. Then performance parameters of these two methods are then compared. We also propose design of 4-bit up/down Asynchronous counter. All the proposed designs are functionally verified using Xilinx ISE simulator with their designs coded in the Verilog HDL.

We report on ongoing work to define a formal semantics for UML-RT suitable for execution and analysis. The paper advocates the use of kiltera as an executable, yet formal, specification language for the high-level description and analysis of complex software systems. kiltera is based on a novel process algebra that extends the π-calculus with time, distribution and execution via an interpreter based on event simulation. We present a textual abstract syntax for a subset of UML-RT and formally define a semantic mapping that explains UML-RT in terms of kiltera. An initial implementation of the semantic mapping is described. Relevant observations are collected, further work is discussed, and relevant related work is reviewed.