Features of embedding non-volatile memory elements in CMOS technology

Recently, non-volatile polymer memories have been researched as a next generation of non-volatile memory because of its simple structure and easy fabrication process. We found that two types of non-volatile polymer memory have different I-V behavior. First Polymer non-volatile memory with metal / oxide / polymer / metal structure But Polymer non-volatile memory embedded Au Nano-crystal shows different I-V behavior. Polymer non-volatile memory shows NDR(Negative Differential Resistance) Region after threshold voltage and low to high current path at increasing positive and negative bias. We can observe NDR(Negative Differential Resistance) Region on Polymer non-volatile memory embedded Au Nano crystal. We fabricated devices three different type to confirm difference Polymer non-volatile memory with metal / polymer / metal structure, metal / oxide / polymer / metal structure and Au nano-crystal embedded Polymer non-volatile memory. First we fabricated Polymer non-volatile memory with metal / PVK(Poly-n-vinyl carbarzole) / metal structure. first type of device shows ohmic I-V behavior. Second type of polymer non-volatile memory has oxide layer between metal and polymer layer. Oxide layer made by O2 plasma treatment(100W RF power, 100SCCM O2 gas flow) after metal layer deposited. Second type of device has same structure as first device except oxide layer. Second type of device shows I-V behavior similar to Resistive Memory. Resistive non-volatile memory shows low to high current path at increasing positive bias and high to low current path at increasing negative bias. I-V behaviors of second device due to effect of oxide layer between metal and polymer layer. Third type of polymer non-volatile memory we embed Au nano-crystal layer in polymer layer. Au nano-crystal layer embedded by curing process. We deposit 5nm Au layer after spin coated PVK(Poly-n-vinyl carbarzole) layer and curing at 300¡É. We can observe NDR(Negative Differential Resistance) Region and different I-V behaviors with other type of device. Finally we fabricated polymer non-volatile memory embedded au nano-crystal by dispersion method to confirm effect of au nano-crystal. We report difference I-V behaviors polymer non-volatile memory with metal / polymer / metal structure and polymer non-volatile memory embedded au nano-crystals

Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU.

Vanadium oxide thin film deposited on Si by atomic layer deposition for non-volatile resistive switching memory devices

A great deal of research has been done on solid-state storage media such as flash memory and non-volatile memory in the past few years. While NAND-type flash memory is now considered a top alternative to magnetic disk drives, different types of non-volatile memory have also begun to appear in the market recently. Although some advocates of storage class memory (SCM) predicted that flash memory would give way to SCM in the very near future, we believe that they will co-exist, complementing each other, for a while until the hurdles in its manufacturing process are lifted and storage class memory becomes commercially competitive in both capacity and price. This demo presents an improved design of In-Page Logging (IPL) by augmenting it with Phase Change RAM (PCRAM) in its log area. IPL is a buffer and storage management strategy that has been proposed for flash memory database systems. Due to the byte-addressability of PCRAM and its faster speed for small reads and writes, the IPL scheme with PCRAM can improve the performance of flash memory database systems even further by storing frequent log records in PCRAM instead of flash memory. We report a few advantages of this new design that will make IPL more suitable for flash memory database systems.

Effect of top electrode material on resistive switching properties of WN based thin films for non volatile memory application

Resistive memory (RRAM) based on a solid–electrolyte insulator is a type of critical nanoscale device with promising potential in non-volatile memory, analog circuits and neuromorphic synapse applications.

structures using different materials will be discussed along with the challenges associated with integration of new materials into a CMOS technology. The discussion of technology will lay the foundation for the subsequent discussions on design techniques for the various non-volatile memory types. Following the design discussions, we will explore different non-volatile memory applications and how the various memory technologies and designs fit within the range of applications. This all day forum encourages open exchange in a closed forum. Attendance is limited and pre-registration is required. Coffee breaks and lunch will be provided to allow a chance for participants to discuss the issues and ask follow-up questions to the forum presenters.

While the memory footprints of cloud and HPC applications continue to increase, fundamental issues with DRAM scaling are likely to prevent traditional main memory systems, composed of monolithic DRAM, from greatly growing in capacity. Hybrid memory systems can mitigate the scaling limitations of monolithic DRAM by pairing together multiple memory technologies (e.g., different types of DRAM, or DRAM and non-volatile memory) at the same level of the memory hierarchy. The goal of a hybrid main memory is to combine the different advantages of the multiple memory types in a cost-effective manner while avoiding the disadvantages of each technology. Memory pages are placed in and migrated between the different memories within a hybrid memory system, based on the properties of each page. It is important to make intelligent page management (i.e., placement and migration) decisions, as they can significantly affect system performance.In this paper, we propose utility-based hybrid memory management (UH-MEM), a new page management mechanism for various hybrid memories, that systematically estimates the utility (i.e., the system performance benefit) of migrating a page between different memory types, and uses this information to guide data placement. UH-MEM operates in two steps. First, it estimates how much a single application would benefit from migrating one of its pages to a different type of memory, by comprehensively considering access frequency, row buffer locality, and memory-level parallelism. Second, it translates the estimated benefit of a single application to an estimate of the overall system performance benefit from such a migration.We evaluate the effectiveness of UH-MEM with various types of hybrid memories, and show that it significantly improves system performance on each of these hybrid memories. For a memory system with DRAM and non-volatile memory, UH-MEM improves performance by 14% on average (and up to 26%) compared to the best of three evaluated state-of-the-art mechanisms across a large number of data-intensive workloads.

This work focuses on Au/HfO2/TiN nonvolatile resistive memory [resistive random access memories (RRAMs)] stacks, where HfO2 is deposited by the atomic layer deposition technique on TiN electrodes. For as-grown RRAMs, no Reset is observed (the structure remains locked in a low resistive state). It is observed that an NH3 plasma treatment of the HfO2/TiN bilayer can restore a Reset stage. X-ray photoelectron spectroscopy analyses showed that the Reset recovery is related to a modification of the HfO2/TiN interface via transformation of the TiON interfacial layer. Thus, postdeposition plasma treatments of the oxide/electrode interface are identified as a valuable tool to improve the switching properties of oxide-based RRAMs.

A nonvolatile organic resistive switching memory based on lotus leaves

Organic–inorganic and polymer-based non-volatile resistive switching memory devices have gained increasing attention because of their excellent data storage capacity, flexibility, low power consumption, durability and widely used in modern electronics. Among the materials, 2D layered nanomaterial and polymer nanocomposites have attracted increasing attention because they can easily be integrated into electronic and optoelectronic devices due to their easy fabrication process, high storage capacity and promising structural properties. Fabrication of bistable memory devices based on organic–inorganic nanohybrid with charge blocking materials and polymer nanocomposite has been broadly elucidated for their extraordinary material properties. Recent enhancement in flexible memory devices based on organic–inorganic semiconductor dispersed in ferroelectric blend polymer has been investigated thoroughly in this review paper. Recent advancement in 2D layered material, ferroelectric polymer and the development of non-volatile memristive devices is extensively explained to understand their importance in flexible devices. Outstanding memory characteristics such as current on/off ratio, Vset, Vreset retention time, endurance of nanohybrid embedded polymer nanocomposite are also discussed meticulously. Next-generation memristor devices based on 2D nanomaterial and ferroelectric polymer with high speed and high density for developing neuromorphic computing system have been demonstrated.

Non-volatile memories (NVM) including flash memories and resistive memories have attracted significant interest as data storage media. Flash memories are widely employed in mobile devices and solid-state drives (SSD). Resistive memories are promising as storage class memory and embedded memory applications. Data reliability is the fundamental requirement of NVM as data storage media. However, modern nano-scale NVM suffers from challenges of inter-cell interference (ICI), charge leakage, and write endurance, which threaten the reliability of stored data. In order to cope with these adverse effects, advanced coding techniques including soft decision decoding have been investigated actively. However, current coding techniques do not capture the physical properties of NVM well, so the improvement of data reliability is limited. Although soft decision decoding improves the data reliability by using soft decision values, it degrades read speed performance due to multiple read operations needed to obtain soft decision values. In this dissertation, we explore coding schemes that use side information corresponding to the physical phenomena to improve the data reliability significantly. The side information is obtained before writing data into memory and incorporated during the encoding stage. Hence, the proposed coding schemes maintain the read speed whereas the write speed performance would be degraded. It is a big advantage from the perspective of speed performance since the read speed is more critical than the write speed in many memory applications. First, this dissertation investigates the coding techniques for memory with stuckat defects. The idea of coding techniques for memory with stuck-at defects is employed to handle critical problems of flash memories and resistive memories. For 2D planar flash memories, we propose a coding scheme that combats the ICI, which is a primary challenge of 2D planar flash memories. Also, we propose a coding scheme that reduces the effect of fast detrapping, a degradation factor in 3D vertical flash memories. Finally, we investigate the coding techniques that improve write endurance and power consumption of resistive memories.

Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density. A prominent characteristic of DRAM-NVM hybrid memory is that it has NVM access latency much higher than DRAM access latency. We call this inter-memory asymmetry. We observe that parasitic components on a long bitline are a major source of high latency in both DRAM and NVM, and a significant factor contributing to high-voltage operations in NVM, which impact their reliability. We propose an architectural change, where each long bitline in DRAM and NVM is split into two segments by an isolation transistor. One segment can be accessed with lower latency and operating voltage than the other. By introducing tiers, we enable non-uniform accesses within each memory type (which we call intra-memory asymmetry), leading to performance and reliability trade-offs in DRAM-NVM hybrid memory. We extend existing NVM-DRAM OS in three ways. First, we exploit both inter- and intra-memory asymmetries to allocate and migrate memory pages between the tiers in DRAM and NVM. Second, we improve the OS's page allocation decisions by predicting the access intensity of a newly-referenced memory page in a program and placing it to a matching tier during its initial allocation. This minimizes page migrations during program execution, lowering the performance overhead. Third, we propose a solution to migrate pages between the tiers of the same memory without transferring data over the memory channel, minimizing channel occupancy and improving performance. Our overall approach, which we call MNEME, to enable and exploit asymmetries in DRAM-NVM hybrid tiered memory improves both performance and reliability for both single-core and multi-programmed workloads.

With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to perform the required store and restore functions. Among various types of NVMs, memristors (a.k.a. RRAM) have several advantages including their small device size, low voltage operation, high speed, and CMOS-compatible fabrication process. In this article, we propose a new 8T1R RRAM-based non-volatile SRAM (NV-SRAM) which adds non-volatility to the SRAM with minimum impact on the Write and Read operations. Simulation at cell-level and array-level have confirmed that the new design performs Read and Write operations at a compatible delay, energy and noise margin as the conventional 6T SRAM, and it is among the best of all reported RRAM-based NV-SRAM designs to our knowledge. In addition, since our 8T1R design uses only one RRAM device per cell, the energy required for storing/restoring the SRAM data to/from the RRAM is significantly reduced by 60%/70% compared to the lowest storing/restoring energy of the previously proposed RRAM-based NV-SRAM designs.

IBM is pioneering an analog in-memory compute technology that promises to considerably reduce the energy consumption needed for AI workloads by performing the computation directly in memory using resistive non-volatile memory (NVM) devices [1]. We have derived requirements for Resistive Processing Unit (RPU) devices that can simultaneously store and process data locally and in parallel, thus providing significant acceleration for deep neural network training [2]. For demonstration of analog in-memory computing applications at scale, the conventional CMOS and memory technologies should be fully leveraged. Most NVM devices available today, however, are optimized for digital applications and do not meet the requirements for RPU. Therefore, co-optimization of hardware, architecture, and algorithm is the key to accommodate the non-ideality of NVM devices [3]. In this talk, we will review the progress in the analog in-memory compute technology and discuss opportunities and remaining challenges.