Fetch Gating Control Through Speculative Instruction Window Weighting

Runahead execution improves processor performance by accurately prefetching long-latency memory accesses. When a long-latency load causes the instruction window to fill up and halt the pipeline, the processor enters runahead mode and keeps speculatively executing code to trigger accurate prefetches. A recent improvement tracks the chain of instructions that leads to the long-latency load, stores it in a runahead buffer, and executes only this chain during runahead execution, with the purpose of generating more prefetch requests. Unfortunately, all prior runahead proposals have shortcomings that limit performance and energy efficiency because they release processor state when entering runahead mode and then need to refill the pipeline to restart normal operation. Moreover, runahead buffer limits prefetch coverage by tracking only a single chain of instructions that leads to the same long-latency load. We propose precise runahead execution (PRE) which builds on the key observation that when entering runahead mode, the processor has enough issue queue and physical register file resources to speculatively execute instructions. This mitigates the need to release and re-fill processor state in the ROB, issue queue, and physical register file. In addition, PRE pre-executes only those instructions in runahead mode that lead to full-window stalls, using a novel register renaming mechanism to quickly free physical registers in runahead mode, further improving efficiency and effectiveness. Finally, PRE optionally buffers decoded runahead micro-ops in the frontend to save energy. Our experimental evaluation using a set of memory-intensive applications shows that PRE achieves an additional 18.2% performance improvement over the recent runahead proposals while at the same time reducing energy consumption by 6.8%.

<div class="section abstract"><div class="htmlview paragraph">A passenger vehicle's front-end structure's structural integrity and crashworthiness are crucial to ensure compliance with various frontal impact safety standards (such as those set by Euro NCAP & IIHS). For a new front-end architecture, design targets must be defined at a component level for crush cans, longitudinal, bumper beam, subframe, suspension tower and backup structure. The traditional process of defining these targets involves multiple sensitivity studies in CAE. This paper explores the implementation of Physics-Informed Neural Networks (PINNs) in component-level target setting. PINNs integrate the governing equations into neural network training, enabling data-driven models to adhere to fundamental mechanical principles. The underlying physics in our model is based upon a force scheme of a full-frontal impact. A force scheme is a one-dimensional representation of the front-end structure components that simplifies a crash event's complex physics. It uses the dimensional and positional parameters of the components, along with their force-displacement curves, to estimate the vehicle's crash pulse. In this work, we have implemented PINNs to generate an optimized force scheme using the historical CAE test data. Using this approach promises to cut short the time and cost that goes into the conventional process of target setting<b>.</b></div></div>

Superscalar processors contain complex control logic in order to extract sufficient instruction level parallelism (ILP). The issue logic is one of the main sources of power dissipation in current superscalar processors. It has been estimated that up to 30% of the energy consumed by a processor is in the issue logic. This paper presents a novel compiler assisted approach to power reduction where we use compiler analysis to pass information to the processor about the number of entries needed, allowing the processor to resize the issue queue dynamically which limit the number of instruction dispatched and resident in the queue reduces the energy consumption without adversely affecting performance. Compared with hardware scheme, our approach is simpler faster and saves more energy. Using the approach we achieve 43.3% dynamic and 28.5% static power savings.

Many Big Data processing applications nowadays run on large-scale multi-tenant clusters. Due to hardware heterogeneity and resource contentions, straggler problem has become the norm rather than the exception in such clusters. To handle the straggler problem, speculative execution has emerged as one of the most widely used straggler mitigation techniques. Although a number of speculative execution mechanisms have been proposed, as we have observed from real-world traces, the questions of when and where to launch speculative copies have not been fully discussed and hence cause inefficiencies on the performance and energy of Big Data applications. In this paper, we propose a performance model and an energy consumption model to reveal the performance and energy variations with different speculative execution solutions. We further propose a window-based dynamic resource reservation and a heterogeneity-aware copy allocation technique to answer the when and where questions for speculative executions. Evaluations using real-world traces show that our proposed technique can improve the performance of Big Data applications by up to 30% and reduce the overall energy consumption by up to 34%.

Architecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification and the correctness criteria for hardware verification. They should define the allowed sequential and relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration of full-scale instruction-set architecture (ISA) semantics with axiomatic concurrency models, either in mathematics or in tools. These ISA semantics can be surprisingly large and intricate, e.g. 100k+\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$+$$\\end{document} lines for Armv8-A. In this paper we present a tool, Isla, for computing the allowed behaviours of concurrent litmus tests with respect to full-scale ISA definitions, in the Sail language, and arbitrary axiomatic relaxed-memory concurrency models, in the Cat language. It is based on a generic symbolic engine for Sail ISA specifications. We equip the tool with a web interface to make it widely accessible, and illustrate and evaluate it for Armv8-A and RISC-V. The symbolic execution engine is valuable also for other verification tasks: it has been used in automated ISA test generation for the Arm Morello prototype architecture, extending Armv8-A with CHERI capabilities, and for Iris program-logic reasoning about binary code above the Armv8-A and RISC-V ISA specifications. By using full-scale and authoritative ISA semantics, Isla lets one evaluate litmus tests using arbitrary user instructions with high confidence. Moreover, because these ISA specifications give detailed and validated definitions of the sequential aspects of systems functionality, as used by hypervisors and operating systems, e.g. instruction fetch, exceptions, and address translation, our tool provides a basis for developing concurrency semantics for these. We demonstrate this for the Armv8-A instruction-fetch and virtual-memory models and examples of Simner et al.

This review aims to provide valuable insights into how energy consumption in magnetic resonance imaging (MRI) and computed tomography (CT) scanners can be effectively monitored, managed, and reduced, thereby contributing to more sustainable medical imaging practices. Demand for advanced imaging technologies such as MRI and CT scanners continues to increase, and understanding the resultant impact on greenhouse gas emissions requires a thorough evaluation of their energy consumption. This review examines the energy monitoring and consumption characteristics of MRI and CT scanners, highlighting potential approaches for energy savings. An overview of MRI and CT principles, hardware components, and their associated energy consumption is provided. After addressing the technical aspects, the hardware and software requirements essential for accurate energy metering are detailed. Baseline measurements of energy consumption data are then provided as a foundation to understand current usage patterns and identify areas for improvement. Ongoing efforts to reduce energy consumption are categorized into 3 main strategies: operations, scanner design enhancements, and active scanning techniques, including accelerated MRI protocols. Ultimately, we emphasize that achieving sustainability in medical imaging requires collaboration across disciplines. By incorporating eco-friendly design in new imaging equipment, we can reduce the environmental impact, promote sustainability, and set a health care industry standard for a healthier planet.

In this paper we propose energy-aware scheduling algorithms that aim to optimize the tradeoff between energy consumption and traditional performance measures such as queue size and delay. We use the power-rate function f(x)= c+xα for x > 0 and f(0)= 0 to model the energy consumption. Scheduling algorithms have been studied in the past for the special case in which the base power c= 0. In general the base power c can be significant. We propose a batch-based scheduling algorithm that can keep the energy consumption to asymptotically optimal while paying for a logarithmic factor in the queue size. Such a tradeoff is best possible. We also characterize the energy-delay tradeoff for a rate-adaptive version of the Weighted Fair Queuing scheduling algorithm.

Recent advances in different instruction set architectures (ISAs) and their implementations have revived the argument on the role of ISAs in the overall performance and energy efficiency of a processor. Many computer architects believe that with current compiler and microarchitecture developments, the choice of ISA is not a decisive matter anymore. On the other hand, some believe that ISAs can still play an important role in the overall performance and energy efficiency of a computer system. Our objective is to compare and contrast ISAs by finding the differences in performance and energy consumption across ISAs and the reasons behind those differences. Our work shows that ISAs affect the performance and energy efficiency of applications differently based on their inherent characteristics.

Architecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification and the correctness criteria for hardware verification. They should define the allowed sequential and relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration of full-scale instruction-set architecture (ISA) semantics with axiomatic concurrency models, either in mathematics or in tools. These ISA semantics can be surprisingly large and intricate, e.g. 100k+ lines for Armv8-A. In this paper we present a tool, Isla, for computing the allowed behaviours of concurrent litmus tests with respect to full-scale ISA definitions, in Sail, and arbitrary axiomatic relaxed-memory concurrency models, in the Cat language. It is based on a generic symbolic engine for Sail ISA specifications, which should be valuable also for other verification tasks. We equip the tool with a web interface to make it widely accessible, and illustrate and evaluate it for Armv8-A and RISC-V. By using full-scale and authoritative ISA semantics, this lets one evaluate litmus tests using arbitrary user instructions with high confidence. Moreover, because these ISA specifications give detailed and validated definitions of the sequential aspects of systems functionality, as used by hypervisors and operating systems, e.g. instruction fetch, exceptions, and address translation, our tool provides a basis for developing concurrency semantics for these. We demonstrate this for the Armv8-A instruction-fetch model and self-modifying code examples of Simner et al.

Summary form only given. Speculative executions help modern processors to expose independent instructions on the fly and accordingly exploit more instruction-level parallelism. However, when incorrect speculations occur, useless work is performed for those incorrectly speculated instructions. This lowers a sustained performance and leads to a significant waste of power. Unlike superscalar processors, simultaneous multithreading (SMT) processors can concurrently execute multiple threads. Thus, they have a chance to control speculative executions by deliberately choosing threads from which instructions will be fetched at each cycle, considering the dynamic characteristics of running threads. We present an efficient front-end mechanism, called SAFE-T (speculation-aware front-end throttling), for scheduling threads in SMT processors. It involves thread prioritizing and throttling; priority given to a thread can be overridden when that thread seems to suffer from an excessive amount of incorrect speculations, therefore preventing instructions from being fetched. Simulation results show that our policy provides an average reduction of 41.6% in the number of wrong-path instructions and improves the instruction throughput by up to 14.5%. A cost-effective implementation for the proposed policy is shown as well.

Many hardware-based defense schemes against speculative execution attacks use special mechanisms to protect instructions while speculative, and lift the mechanisms when the instructions turn non-speculative. In this paper, we observe that speculative instructions can sometimes become Speculation Invariant before turning non-speculative. Speculation invariance means that (i) whether the instruction will execute and (ii) the instruction's operands are not a function of speculative state. Hence, we propose to lift the protection mechanisms on these instructions early, when they become speculation invariant, and issue them without protection. As a result, we improve the performance of the defense schemes without changing their security properties. To exploit speculation invariance, we present the InvarSpec framework. InvarSpec includes a program analysis pass that identifies, for each relevant instruction i, the set of older instructions that are Safe for i-i.e., those that do not prevent i from becoming speculation invariant. At runtime, the InvarSpec micro-architecture loads this information and uses it to determine when speculative instructions can be issued without protection. InvarSpec is one of the first defense schemes for speculative execution that combines cooperative compiler and hardware mechanisms. Our evaluation shows that InvarSpec effectively reduces the execution overhead of hardware defense schemes. For example, on SPEC17, it reduces the average execution overhead of fence protections from 195.3% to 108.2%, of Delay-On-Miss from 39.5% to 24.4%, and of InvisiSpec from 15.4% to 10.9%.

The possibility of using renewable feedstocks for biodiesel production and reducing gas emissions makes it an attractive large-scale substitute to traditional fossil diesel. Although renewability is one of the main driving forces in biodiesel use, traditional production routes employ methanol as the transesterification agent, a chemical generated from fossil carbon. Aiming at further improving biodiesel’s sustainable performance, the replacement of methanol by ethanol has been proposed. Use of the ethylic production route could further reduce CO2 emissions, energy consumption and generate more jobs. The objective of this study is to unveil whether substituting methanol for ethanol does indeed result in a less carbon and energy intensive production chain while also increasing job generation and decreasing social strife. To assess production chain performance a lifecycle approach was used composed by: (i) Data assemblage from literature to represent the ethylic/methylic biodiesel systems; (ii) Construction of quantitative indicators to compare material and energetic flows; and (iii) Principal Component Analysis (PCA) for data interpretation and relevance ranking of calculated social/environmental indicators. Focus was given to CO2 emissions, energy consumption and social aspects of sustainability. Results show that use of ethanol does indeed reduce CO2 emissions, due to extra agricultural carbon sinks in the production chain but increases energy consumption and energy loss. Methanol also resulted in a chain with higher average wages, more jobs generated and less forced labor cases but with a higher accident rate and a high salary disparity. PCA showed that carbon intensity is one of the most important environmental metrics while energy consumption was considered secondary, but the high correlation between these aspects highly impact chain sustainability. PCA also greatly differentiated agricultural and industrial links of respective production chains, with industrial links being governed by CO2 emissions and process safety and agricultural links by water consumption, land use and energy loss. A distinct tradeoff was seen between environmental and social considerations of sustainability and between carbon intensity and energy consumption reductions. As a result, substitution is only justified in scenarios in which CO2 emissions outweigh energy intensity and social aspects.

Various preidentification instructions have been proposed to reduce eyewitness misidentifications by promoting conservative responding. According to the classic signal detection model, such instructions should shift decision criteria without affecting discriminability-the ability to distinguish innocent from guilty suspects. Yet, in prior research, while two types of instructions did make participants respond more conservatively, one type of instruction decreased discriminability and another increased discriminability. Across four experiments-three conducted online and one in the field-we tested the effects of different instructional methods on eyewitness responding in both lineup and showup procedures. We found that while certain instructions consistently induced more conservative responding, they sometimes decreased and never increased discriminability. We attribute this pattern to instructional variance: participants likely interpreted and complied with the instructions to varying degrees, introducing noise that lowered discriminability. Notably, identifications made with high confidence were associated with much more conservative responding than any instruction alone, suggesting that conservative responding is best achieved by collecting confidence rather than by instructing eyewitnesses to respond conservatively. Finally, the confidence-accuracy relationship was stronger in our field showup using live actors than in the corresponding online version, underscoring the need for more research in the field to better understand eyewitness identification performance. (PsycInfo Database Record (c) 2026 APA, all rights reserved).

In the embedded domain, memory usage and energy consumption are critical constraints.Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.

This study presents an empirical investigation into the energy consumption of discriminative and generative AI models within real-world MLOps pipelines. For discriminative models, we examine various architectures and hyperparameters during training and inference and identify energy-efficient practices. For generative AI, large language models (LLMs) are assessed, with a focus primarily on energy consumption across different model sizes and varying service requests. Our study employs software-based power measurements, ensuring ease of replication across diverse configurations, models, and datasets. We analyse multiple models and hardware setups to uncover correlations among various metrics, identifying key contributors to energy consumption. The results indicate that, for discriminative models, optimising architectures, hyperparameters, and hardware can significantly reduce energy consumption without sacrificing performance. For LLMs, energy efficiency depends on balancing model size, reasoning complexity, and request-handling capacity, as larger models do not necessarily consume more energy when utilisation remains low. This analysis provides practical guidelines for designing green and sustainable ML operations, emphasising energy consumption and carbon-footprint reductions while maintaining performance. This paper can serve as a benchmark for accurately estimating total energy use across different types of AI models.