Field modifiable architecture with FPGAs and its design methodology

This paper deals with the system of agents treated as a concurrent modular system, which is able to support the designer in solving complex design tasks. The behavior of design agents is modeled by sets of grammar rules. Each agent manages a graph grammar and a database of facts concerning the subtask for which it is responsible. The course of designing is determined by the interaction between cooperating specialized agents. The design context is expressed by the environment in which agents act and predicates describing design criteria. The organization, design methodology, and a semantic model of a grammar-based multiagent design system are presented. The notions of a valid design solution and a design solution consistent with the design criteria are also introduced. The proposed approach is illustrated by the example of designing a house estate.

Design methods support the derivation of alternative design solutions, and based on product requirements, it provides a platform for the evaluation and selection of appropriate solutions. Because of the driving needs of design and manufacturing industries and also the quest to remain competitive, several design methodologies aimed at addressing aspects of industrial requirements have emerged. This study identifies current best practice design methodologies and their performance when compared with current trends in design and manufacturing. Based on the review, the strengths and weaknesses of current methods are highlighted and used as the platform to support the recommendation for an integrated design and manufacturing methodology. The integrated design and manufacturing methodology rest on the strengths of product design, cost engineering, enterprise and process simulation modelling techniques. This method can help in the (re)design and (re)engineering of products and processes for better cost indications; help determine appropriate manufacturing paradigms; perform virtual experiments to understand implication of production volume changes on designs and flexibility needs in production systems.

This paper describes the experience of Petrobras in the design, installation and operation of deepwater mooring systems incorporating high efficiency polyester fiber ropes. These ropes have been used now for more than 12 years in catenary and taut configurations to moor drilling and production units as well as storage and offloading facilities. The paper provides a history of the development of this technology, highlighting the key issues involved in introducing in mooring systems a component that has non-linear visco-elastic behavior. Differences to all steel systems in terms of: behavior, failure modes and design criteria and procedures are discussed. The paper presents the life cycle management strategy adopted by Petrobras in the early years of the use of this technology and its evolution that have guaranteed that the only failure mode observed over all these years was mechanical damage. It is expected that this paper shows that the use of polyester (polyethylene terephthalate) ropes in deepwater moorings is a mature technology. Introduction In the mid 80's Petrobras was drilling in Campos Basin in water depths around 600m and producing in depths around 400m. Mooring systems were all based on chain, wire rope and drag embedment anchors. Increasing water depths indicated that all steel systems would become anti-economical due to the reduction in restoring efficiency. Initial studies were based in using synthetic fiber ropes as extension wires in the mid-catenary. Since compliance to wave induced motions would be given by the geometry of the steel components the fiber rope should have stiffness similar to a steel wire rope. Therefore aramid ropes were the first to be considered (Riewald, 1986). Cost considerations led Petrobras and the US Navy (Karnosky & Liu, 1988) to start studying the use of polyester fiber ropes for moorings. It was also devised that, in deepwater, the axial compliance of polyester ropes could provide enough compliance so that a long catenary might not be required (Baxter, 1987). The use of polyester ropes in permanent moorings was a big challenge for several reasons, the most obvious one being establishing design methodologies and criteria for all possible failure modes. Since most large diameter fiber ropes were not optimized for tension and axial fatigue performance (Parsey, 1983)), it was also necessary to further develop rope constructions and generate enough data on the performance of these ropes. Results of a comprehensive study on the use of fiber ropes for deepwater moorings were presented in 1992 (Chaplin & Del Vecchio, 1992). Full details of the study, including assessment of failure modes, load-elongation behavior, design methodologies and criteria were produced (Del Vecchio, 1992). Since the study was partially based in model ropes, confirmation of load-elongation behavior in full scale and additional data on fatigue performance were obtained in the following years and incorporated in the type approval process of the ropes. Field trials were conducted in 1995 to assess installation procedures.

COMIND is a tool for conceptual design of industrial products. It helps designers define and evaluate the initial design space by using search algorithms to generate sets of feasible solutions. Two algorithm visualization techniques, Kaleidoscope and Lattice, and one visualization of n-dimensional data, MAP, are used to externalize the machine's problem solving strategies and the tradeoffs as a result of using these strategies. After a short training period, users are able to discover tactics to explore design space effectively, evaluate new design solutions, and learn important relationships among design criteria, search speed, and solution quality. We thus propose that visualization can serve as a tool for interactive intelligence, i.e., human-machine collaboration for solving complex problems.

PurposeThe generic design environment for a flexible printed‐circuit board assemblies (PCBA) remanufacturing cell contains four interrelated complex design domains. Mechanical design domains are really complex and the use of well‐proven mechanical product design methodologies does not help the designer. Hence, this paper aims to develop a generic systematic design methodology for a flexible PCBA remanufacturing cell.Design/methodology/approachThe study investigates the use of conventional mechanical product design techniques for the design of a flexible PCBA rework (remanufacturing) cell. It indicates problems and the weaknesses when conventional product design techniques are used for the development of flexible manufacturing systems (FMS). It then provides a new systematic mechanical design methodology for designing a flexible PCBA rework (remanufacturing) cell. The design methodology is intended to be generic in order to apply successfully to any FMS design.FindingsConventional product design methodology cannot be used directly for the design of a flexible PCBA remanufacturing cell. Hence, two design methodologies were developed: the generic FMS mechanical design methodology and a specific FMS design methodology for a PCBA rework cell. The first one was developed based on the tasks of the conventional product design process integrated with new design tools. The generic design methodology was then extended to obtain the second methodology for a PCBA rework cell design. Both of the methodologies were applied to a flexible PCBA rework cell design problem. Both design methodologies eliminated unusable design solutions at the early design stages of the conceptual design process and made the design process easier.Practical implicationsThe generic and specific design methodologies provide a better design environment, even for less specialized FMS designers.Originality/valueThe design methodologies may help for the commercialization of a flexible PCBA remanufacturing cell that may be used for SM rework and assembly.

The following investigation on flip-flop circuits was originally undertaken to determine if a reliable flip-flop circuit could be designed to operate from a low supply voltage using tubes that are presently available and in production. The reason for designing the circuit to operate from a low supply voltage is to reduce the required power consumption of such information storage devices to a minimum and to provide a low d-c level output. The low d-c level output voltages of the two stable states of the circuit and the low flip-flop power dissipation enables an entire computer to operate from one regulated power supply rather than the numerous regulated supplies required by most computers. The low power dissipation is also essential since the reliability of germanium diodes and other heat sensitive components is greatly increased as their operating temperature is decreased.

9 - Design methodology

A very large-scale integrated (VLSI) circuit is commonly defined as a single chip which contains more than 100,000 devices. This year (1980) several industrial electronic firms are designing IC’s with device counts of more than 100,000. These circuits are either in initial design or are possibly in initial prototype production. Generally, the NM0S technology is being used with a minimum feature size in the 1–2 micron range. The design methodology and the computer aids used in the VLSI design, in general, are those that are also being used in today’s LSI production or are relatively modest extensions of these methodologies and computer aids for design.

Information portals are usually created to support the integration of migrants into a host country. However, the information-seeking process can be exhausting, cumbersome and even confusing for migrants as they must cope with time-consuming information overload while searching desired information from lists of documents. Chatbots are easy-to-use, natural, and intuitive, and thus could support information-seeking. There is a lack of research that engages and empowers migrants and other stakeholders as co-design participants in chatbot development. We explored how migrants can be empowered in designing a chatbot that supports their social integration. Using a co-design approach, we conducted a series of activities with migrants and other stakeholders (i.e., online questionnaires, empathy probes, surveys, and co-design workshops) to first understand their expectations regarding chatbots, and then co-design a personality-driven chatbot. We found that chatbot personality can drive co-designing a chatbot as design goals, design directions, and design criteria.

Single Electron Transistor (SET) is a nanoelectronic device that operates under the controlled mode of tunneled individual electrons. In this paper, a comparative analysis was performed employing SET based D-Flip flop with conventional logic D-flip flop. SET is eminent nanoscale devices that have low power dissipation, high speed and performance. The flip flop design was simulated using SIMON simulator and the stability of its operation was analyzed applying the Monte-Carlo method that represented stability with low power dissipation and matched the functionality of traditional CMOS devices.

Coupling Of Synthesis And Layout: Challenges And Solutions

This work is concerned with the study of the analog properties, in particular in terms of gain and noise performance, of MOSFET devices belonging to a 65 nm CMOS technology. Silicon vertex detectors at the next generation colliders will be read out by means of front-end electronics based on fabrication processes with minimum feature size in the 100 nm range. Among the more scaled CMOS technologies, the 65 nm node is starting to be considered by integrated circuit designers for the development of Application Specific Integrated Circuits in detector applications. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. Data obtained from the measurements of devices provide a powerful tool to establish design criteria in this nanoscale CMOS process for detector front-ends. A comparison with data coming from less scaled technologies, such as 90 and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

We had reported TTRAM (Morishita, 2005) and ET <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> RAM (Arimoto, 2006) which are high-density capacitor-less SOI-CMOS compatible memory IP's. A platform design methodology becomes the main stream in SoC world because the system integration progress and complexity requires the implementation of many lands of IP's and induces the longer design turn around time and design cost up. This time, we have up-graded ET <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> RAM with scalable function named SETRAM (scalable enhanced twin-transistor RAM). This memory IP can be applied to the many kinds of applications by the verify control technique with compact ABC (automatic body control) sense amplifier. The scalable functions are, for example, 263MHz high speed random cycle memory to replace the high density on chip SRAM, 79mW/4Mb lower active power dissipation for mobile application, 453MHz data transfer of page/burst mode for cache memory and graphics memory applications and lower stand-by current mode of 5 sec data retention time. These are also supported as the programmable functions. The SETRAM can provide the scalable memory IP's in SoC platform on SOI devices and can improve the performance of many future applications

A novel selective compliant actuator

Microwave imaging based on UWB pulses can detect breast cancer, even at an initial stage. To favor the adoption of this method in screening campaigns, it is necessary to replace the expensive and bulky RF instrumentation used so far with ad-hoc designed circuits and systems. In this paper we report on a possible design solution that aims to integrate many of the components in CMOS integrated circuits. Having this as final goal of our MICENEA project, we preliminary assessed the system-level performance of a few critical blocks of the UWB receiver: a slot antenna, the LNA, and the track-and-hold amplifier, the latter two implemented in a CMOS 130nm technology. We developed a simulator that allows us to mix blocks described at circuit-level with blocks described at behavioral level and that simulates a full system, from UWB source to the breast image. We can observe the effect on the final image of non-idealities, like circuit-level limitations and various noise sources, as well as evaluate image quantitative metrics. We report results that show very good system-level performance-only marginally affected by such non-idealities-and that prove the effectiveness of our circuit-level choices and design methodology.