Field programmable gate array processing for an improved low-light-level imaging system with higher detection sensibility.

Contents-addressable memory (CAM) is a special memory that searches the input data with the entire pre-loaded database and generates corresponding address information. CAMs are advancing to be a core technology in computer networking systems. As field programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate CAM on FPGA is increasing. FPGA-based CAMs are divided into three categories of implementation: register-based, block RAM (BRAM)-based, and distributed RAM-based CAM. However, they come with a cost of excessive resource usage. Besides, the collision ratio is high in FPGA-based CAMs, leading to data loss and failure to produce accurate addresses. Synchronous dynamic random-access memory (SDRAM)-based CAMs, benefiting from the features of high density and low price of SDRAM, solve the limitations of FPGA’s on-chip resources. This paper proposes a data collision CAM hardware implementation using modern FPGA’s off-chip SDRAM for data storage. The hardware architecture is customized for massive lookup tables and resource-saving. Furthermore, the architecture is parameterized, which is better for integration. The synthesis results and comparisons show significant advancement compared to other FPGA-based CAM implementations by total reduction of on-chip RAM. The novel architecture shows remarkable improvement in the memory depth and width with the capacity of 128 Mbyte lookup table.

Synchronous dynamic random access memory Synchronous dynamic random access memory (SDRAM) (SDRAM) has been widely used in various systems. From DDR1 to GDDR5, the operating speed has been rapidly increased to keep pace with the performance of application system. Up to now, 7 Gb/s/pin GDDR5 is the fastest SDRAM adopted in graphics cards (R. Rho et al., IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 120–133, 2010; T.-Y. Oh et al., IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 120–133, 2011; D. Shin et al., IEEE Symp. on Very Large Scale Integr. Circuits Dig. Tech. Papers, pp. 138–139, 2009). However, the DRAM’s core speed cannot be increased due to technical limits. Other approaches are required to solve the limited core speed. In addition, scaling limits and increased lithography costs make it hard for DRAM vendors to increase the density of DRAM. Wide I/O DRAM is one alternative type of memory, as is TSV-based stacked memory. In this chapter, we introduce the fundamentals of high-speed DRAM operation. We do not cover the basic knowledge of complementary metal-oxide semiconductor (CMOS) circuits including design, layout, and simulation.

A highly efficient Synchronous Dynamic Random Access Memory (SDRAM) controller supporting variable-length burst access and batch process for discrete reads is proposed in this paper. Based on the Principle of Locality, command First In First Out (FIFO) and address range detector are designed within this controller to accelerate its responses to discrete read requests, which dramatically improves the average Effective Bus Utilization Ratio (EBUR) of SDRAM. Our controller is finally verified by driving the Micron 256-Mb SDRAM MT48LC16M16A2. Successful simulation and verification results show that our controller exhibits much higher EBUR than do most existing designs in case of discrete reads.

After analyzing the principle of SDRAM,a Synchronous Dynamic Random Access Memory(SDRAM) controller used in large-array CCD image real-time display system was designed with parameterization design concept.It was implemented by VHDL hardware description language and had a simple interface.Then the SDRAM controller was successfully used in real-time display system of large-array CCD image and worked very well.

Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

System security is an increasingly important design criterion for many embedded systems. These systems are often portable and more easily attacked than traditional desktop and server computing systems. Key requirements for system security include defenses against physical attacks and lightweight support in terms of area and power consumption. Our new approach to embedded system security focuses on the protection of application loading and secure application execution. During secure application loading, an encrypted application is transferred from on-board flash memory to external double data rate synchronous dynamic random access memory (DDR-SDRAM) via a microprocessor. Following application loading, the core-based security technique provides both confidentiality and authentication for data stored in a microprocessor's system memory. The benefits of our low overhead memory protection approaches are demonstrated using four applications implemented in a field-programmable gate array (FPGA) in an embedded system prototyping platform. Each application requires a collection of tasks with varying memory security requirements. The configurable security core implemented on-chip inside the FPGA with the microprocessor allows for different memory security policies for different application tasks. An average memory saving of 63% is achieved for the four applications versus a uniform security approach. The lightweight circuitry included to support application loading from flash memory adds about 10% FPGA area overhead to the processor-based system and main memory security hardware.

To meet the application needs of universal platforms such as broadband, high-frequency target recognition and tracking radar, imaging radar, etc., we design and demonstrate a multi-channel digital optical transceiver and processing microsystem. The multi-channel digital optical transceiver and processing microsystem includes a high-performance signal processing SIP (system in a package) circuit and a four-channel parallel integrated digital optical transceiver module adopting BGA980 packaging pattern, which can implement digital circuit preprocessing and high-speed optical transmission. The high-performance signal processing SIP circuit integrates one FPGA (Field Programmable Gate Array), one flash memory, one DDR3 SDRAM (Synchronous Dynamic Random-Access Memory), one EMMC (Embedded Multi Media Card), one ADC (Analog-to-Digital Converter) and one DAC (Digital-to-Analog Converter). The four-channel parallel integrated digital optical transceiver consists of transmitting end and receiving end, with a single channel optical transmission rate of 10.3125Gbps. The transmitting end of the module is composed of an VCSEL array laser and its driven control circuit, while the receiving end is composed of a detector array and TIA (Trans- Impedance Amplifier) circuit. The module adopts LCC48 surface mount packaging form and transmits data through flat ribbon fiber bundles via MT type interface. The high-performance signal processing SIP circuit and the four-channel parallel integrated digital optical transceiver module achieve control and data transmission through the GTX (Gigabyte Transceiver) interface in the FPGA chip. We demonstrate a transmission loop experiment to test the transmission rate and transmission quality, using the IBERT (Integrated Bit Error Ratio Tester) module in the vivado software. When the link rate parameter in FPGA is set to 6.25Gbps, the result in vivado shows that the link is normal and the eye diagram opens well. The measured bit error ratios of the transmitting end and the receiving end are 1.86×10^-12 and 2.20×10^-12 respectively. This type of microsystem has advantages of anti-interference, broadband, high-frequency, small size, and high transmission rate, which plays an important role in fields such as electronic antagonism.

The radiation tolerant intelligent memory stack (RTIMS), suitable for both geostationary and low Earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained "flight-like" module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm /spl times/ 42.7mm /spl times/13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

In recent years, wavelet transform is applied to ECG signal processing for ECG characteristic points detection. However, most of the published algorithms are offline algorithms running in personal computer. This paper proposes the QRS complex detection design in field programmable gate array (FPGA). Although there are a few papers about implementing QRS detection design in FPGA most of them employ embedded processor in FPGA, resulting in that the parallel processing advantage of FPGA can not be fully utilized. The proposed design utilizes the parallelism of FPGA and can operate in the maximum throughput of 57.534 MSa/s in real time, while the sampling rate of input ECG signal is only several hundred samples per second.

Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA shows a powerful potential for packet processing. By supporting the P4 language with FPGA processing, network researchers can create customized FPGA-based network functions and execute network tasks on accelerators directly connected to the network. A feature of the P4 language is that it is stateless; however, the FPGA implementation in this research requires state information. This is accomplished using P4 externs to describe the stateful portions of the design and to implement them on the FPGA using High-Level Synthesis (HLS). This paper demonstrates using an FPGA-based SmartNIC to efficiently extract source-destination IP address information from network packets and construct anonymized network traffic matrices for further analysis. The implementation is the first example of the combination of using P4 and HLS in developing network functions on the latest AMD FPGAs. Our design achieves a processing rate of approximately 95 Gbps with the combined use of P4 and High-level Synthesis and is able to keep up with 100 Gbps traffic received directly from the network.

Dynamic random access memory (DRAM) devices are used to handle data transfer to and from the microprocessors in a computer or server. Traditionally, the speed of the memory devices has lagged behind that of the microprocessors. With the advent of high-speed microprocessors such as Intel's Pentium 4 and AMD's Athlon, the speed of DRAM has also increased from below 100 MHz to near 1 GHz. At the same time, memory chip density has increased from 512 Kbit to 256Mb or higher. To package the new generation of high-density devices, new packaging technology such as chip scale package (CSP) is being applied to replace SOJ and TSOP packages. This paper reviews the progress in memory technology and its applications, including Synchronous Dynamic Random Access Memory (SDRAM), Rambus DRAM (RDRAM), and Double Data Rate (DDR) SDRAM. Packaging technology used for these devices, including conventional TSOP, stacked TSOP and chip scale packages such as μBGA and memory BGA (mBGA) for Rambus and DDR are discussed. The surface mount technology (SMT) manufacturing process of Dual In-line Memory Modules (DIMM) is described. Experimental results on solder printing and reflow profile condition optimization for the DIMM modules are discussed in detail by comparison of the resulting microscopic solder joint grain structures.

This work presents a novel hardware implementation of a levelset algorithm for carotid lumen segmentation in computed tomography. We propose to use a field programmable gate array (FPGA) to iteratively solve the underlying finite difference scheme. A FPGA processor can be programmed to have a dedicated hardware architecture including specific data path and processor core design with different types of parallelizations which is fully tailored and optimized toward its application. The method has been applied to ten carotid bifurcation of six stroke patients and the results have been compared to the results obtained from the same method implemented in C++. Visual inspections revealed similar segmentation results. The average computation time in software was 1663 ± 86 seconds, the computation time on the FPGA processor was 28 seconds yielding approximately a 60-fold speed-up which to our knowledge has been unmmatched before for this class of algorithms.

Chapter 14 - Embedded Processing Cores

In this paper, we will present results from testing commercially-available synchronous dynamic random access memory (SDRAM) in high-energy protons and neutrons. Broad spectrum neutron tests were conducted at Los Alamos National Laboratory's Los Alamos Neutron Science Center (LANSCE) Irradiation of Chips and Electronics (ICE) House in October 2010. Mono-energetic proton tests were conducted at the Massachusetts General Hospital Burr Center in May 2011.

The main objective of this work is to improve the performance of Multilevel Inverter by using the novel LS-PD- PWM and controlling technique instead of the existing approach. The proposed work focus on closed loop controller such as existing PI and Fuzzy Logic Controller for resistive load with Multilevel Inverter. The proposed Asymmetric fifteen level Inverter offers less THD and high frequency than the Asymmetric nine level inverter. Asymmetric multilevel inverter is used to reduce the switching losses and THD. In this work is the generation and implementation of Pulse Width Modulation (PWM) techniques using Field Programmable Gate Array (FPGA) for Multilevel Inverter. PWM can be generated via Microprocessors, Microcontroller, FPGA and DSP Processors. Higher density Programmable Logic Devices (PLD) such as FPGAs can be used to amalgamate large amounts of logic into a single Integrated. Pulse width modulation (PWM) is generally used in power converter control. To generate LS-PD- PWM by using FPGA, this occupies less memory capacity and accurate than conventional one. An efficient PWM generation technique is performed using FPGA for lower frequency applications. Simulation and synthesis is done by ModelSim6.3c and Xilinx10.1. Further, the Implementation is carried out by FPGA Spartan3 Xc3s50. Key Word: PWM, FPGA, PLD (Programmable Logic Devices), LS-PD-PWM