Fine-Grained Scheduling in Heterogeneous-ISA Architectures

Heterogeneous-ISA multi-core architectures have emerged as a promising design paradigm given the ever-increasing demands on single threaded performance. Such architectures comprise multiple cores that differ not just in micro-architectural parameters (e.g., fetch width, ROB size) but also in their Instruction Set Architectures (ISAs). These architectures extract previously latent performance gains by executing different phases of the program on the core (and ISA) best suited to it, as opposed to executing the entire program on a single ISA. In such a computing paradigm, maximum performance is only extracted when we ensure that at every point in the program’s execution, the program runs on the core best suited to it. In this work, we propose a migration framework that practically and accurately decides when to migrate the program across different cores (and ISAs) to extract maximum performance gains. Under the covers, this framework combines a regression based performance modelling technique with a greedy scheduling algorithm. Our performance modelling technique leverages hardware performance counters prevalent in all major processors today to accurately estimate the performance of the program on different ISAs to within an error of 6%. Putting it together with our greedy scheduler enables our framework to achieve single thread performance speedups of 29.6% with respect to a baseline single ISA heterogeneous architecture.

Summary form only given. Workload characterization relies heavily on robust and powerful tools to quickly and accurately gather and analyse large amounts of data about program executions. Valgrind is a dynamic binary instrumentation framework for building program analysis tools. Valgrind is best known for a tool, Memcheck, that finds memory errors common in C and C++ programs, but its ability to instrument every instruction and system call a program executes, and inspect every value a program manipulates, without slowing down program execution excessively, makes it an excellent platform for buildings tools suitable for workload characterization. In this tutorial, we introduce Valgrind, describing how you can use it to create powerful tools for doing profiling and trace collection, and to help characterize how workloads affect different machine aspects such as instruction set architecture, the memory hierarchy, and I/O. Valgrind provides powerful analysis tools without excessive slow-down, which allows very large workloads to be analysed easily. Valgrind is open-source (GPL) software, available on x86/Linux, AMD64/Linux, PPC32/Linux, PPC64/Linux, and work is underway to support other platforms. Valgrind tools are regularly used by the developers of many software packages, such as Firefox, OpenOffice, KDE, GNOME, MySQL, Perl, Python, PHP, Samba, RenderMan, SAS, The GIMP, Unreal Tournament, Squid, plus many scientific applications

VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set architectures. Programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the same machine model with different number of functional-units. This paper describes an architecture, named dynamically trace scheduled VLIW (DTSVLIW), which can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility. Some preliminary performance measurements of the DTSVLIW, obtained with an execution-driven simulator running the SPECint95 benchmark suite, are also presented.

Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single-threaded performance coupled with high multi-threaded throughput and higher performance-per-watt. A significant portion of the commercial multicore heterogeneous processors are likely to have a common instruction set architecture( ISA). However, due to limited design resources and goals, each core is likely to contain ISA extensions not yet implemented in the other core. Therefore, such heterogeneous processors will have inherent functional asymmetry at the ISA level and face significant software challenges. This paper analyzes the software challenges to the operating system and the application layer software on a heterogeneous system with functional asymmetry, where the ISA of the small and big cores overlaps. We look at the widely deployed Intel® Architecture and propose solutions to the software challenges that arise when a heterogeneous processor is designed around it. We broadly categorize functional asymmetries into those that can be exposed to application software and those that should be handled by system software. While one can argue that new software written should be heterogeneity-aware, it is important that we find ways in which legacy software can extract the best performance from heterogeneous multicore systems.

This paper presents a novel vision chip architecture based on pixel-neighborhood-level parallel processing. In the architecture, an 8-b RISC processing core is embedded in an 8×8 array of digital pixel sensors on the same focal plane. These neighborhood processors (NPs) are tiled in a 2-D array to form the final imager resolution. Program execution is carried out in parallel across the array of pixel-neighborhood processing cores, allowing for direct scalability in terms of resolution, without reduction in processing speed or frame rate. To accomplish this, a compact, low-complexity NP architecture along with a general purpose, 8-b instruction set has been designed and implemented. A prototype vision chip containing an 8×10 array of NPs with a 64×80 resolution has been designed and fabricated in a 0.13-μm 1P8M CMOS fabrication process. The system is reprogrammable and can perform a wide range of image and video processing tasks. Several example algorithms are implemented and tested on the single-chip vision system to demonstrate the functionality of pixel-neighborhood-level parallelism, including 1000-frames/s object tracking.

Fault-injection experiments on the instruction-set architecture level are commonly used to analyze embedded software's susceptibility to hardware faults, typically involving a vast number of experiments with systematically varying fault locations and times. Determinism and high performance are the predominant requirements on fault-injection platforms. Injecting faults into a real embedded hardware platform instead of a simulator is favorable for both workload execution speed and result accuracy. The most performance-critical part of such a fault-injection platform is the “fast forward” operation, which executes the target machine code without faults until the exact dynamic instruction is reached at which the execution must be stopped to inject the next fault. Unfortunately, most embedded CPUs do not support this operation efficiently. In this paper we present an approach that speeds up fast-forwarding significantly for most workloads with minimal requirements on hardware support. Based on a previously recorded instruction trace - which is needed for systematic fault-injection experiment planning anyways - we use standard debugging hardware to advance to a chosen point in program execution with a minimal number of steps. We evaluate our FAIL* tool platform with two MiBench benchmark categories, and improve experiment throughput by up to several magnitudes compared to similar fault-injection tools in the field.

Computer architecture is an important subject for informatics and electrical engineering courses. However, students display some difficulties in this subject, mainly due to the lack of educational tools that are intuitive, versatile and graphical. Existing tools are not adequate enough or are very specific. In this paper, an educational MIPS simulator, DrMIPS, is described. This tool simulates the execution of an assembly program on the CPU and displays the datapath graphically. Registers, data memory and assembled code are also displayed and a “performance mode” is also provided. Both unicycle and pipeline implementations are supported and the CPUs and their instruction sets are configurable. The tool is currently available for PCs and Android tablets, and is fairly intuitive and versatile on both platforms.

ENERGY efficient computing used to be a concern only for designers of untethered computer and mobile communication systems, where battery size and recharge intervals limited their usefulness. In the past few years, the importance of reducing energy has become a central concern for designers of tethered computers as well because of the power limitations of a standard household power outlet and because they are often deployed in large groups, in the case of server farms. To address the research issues that arise in energy efficient computing, the US Defense Advanced Projects Agency began a program several years ago under the heading Power Aware Computing and Communications (PAC/C). This has led to a wide range of new developments in energy efficient computing and communications. This special issue solicited original papers from, but not restricted to, researchers in the PAC/C program. Our goal was to show the wide range of computer related research that is concerned with minimizing energy consumption in one way or another. Our lead-off paper, “Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages,” employs genetic algorithm for module selection and scheduling under the constraints of power and area. The next paper, “Charge-Recovery Computing on Silicon,” presents an overview of energy-recovering systems, focusing on recent developments. The third paper, “A Holistic Approach to Designing Energy-Efficient Cluster Interconnects,” looks at interconnecting networks of computers and addresses the problem of designing the interconnects to be energy-efficient. The fourth paper, “Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors,” focuses on the microarchitectural level and proposes and analyzes a clustered loop buffer for VLIW-style processors. The analysis shows that such buffers are able to generate a significant amount of energy savings. The fifth paper in our series, “Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors,” moves to a higher level of abstraction and proposes a fast and efficient approach for designing and estimating energy consumption for single chip heterogeneous multiprocessors—a common platform for mobile system. The sixth paper, “An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs,” returns to the microarchitectural level. It proposes a design time instruction set minimization to reduce instruction cache power. The seventh paper, “Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations,” looks at the application level, specifically the power-performance of motion detection in an image processing application. The eighth paper, “Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes,” is a tutorial paper on sensor networks with special emphasis on their power requirements. The penultimate paper, “A Speculative Control Scheme for an Energy-Efficient Banked Register File,” again returns to the microarchitectural level and shows how low power register files can be constructed from smaller faster banks of registers. The last paper, “GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks,” proposes an adaptive scalable architecture targeted toward algorithm-specific tasks in which power is a constraint. The architectural model derives its scalability from a set of Globally Asynchronous and Locally Synchronous (GALS) building blocks.

Improving System Predictability and Performance via Hardware Accelerated Data Structures

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core x86 host machine for as many as 2,048 target processors whilst exhibiting minimal and near constant overhead, including memory considerations.

An important issue in the execution of programs on multiprocessor systems with non-uniform memory access times is data locality. Most of the dynamic scheduling algorithms deal well with load balance, but fail to take locality into account and, therefore, behave poorly on NUMA systems. In this paper we present a scheduling algorithm which has as its objective to increase data locality, and therefore performance, in problems based on elimination trees. We applied this scheduling to the modified Cholesky factorization as a case study. Experimental results on the SGI O2000 are shown.

Dear SCPE Reader, We present a selection of papers which are extensions of papers presented at the 7-th International Symposium on Parallel and Distributed Computing, 1–5 July 2008, in Krakow, Poland. The motivation for publishing the selection in the SCPE Journal was, on the one hand, to present the flavour of the research reported at the conference and on the other hand to present some of the most relevant topics currently focused on the research on parallel and distributed computing in general. The selection contains only 6 papers out of about 60 presented at the conference, and thus, is far from covering all relevant topics represented at the ISPDC 2008. This is because not all of the invited authors were patient enough to accept a fairly long paper publishing process. Nevertheless, we hope that the presented papers will bring you closer to the research covered by the ISPDC conferences and will encourage you to participate in future ISPDC editions. The first paper ``The Impact of Workload Variability on Load Balancing Algorithms'' is by Marta Beltran and Antonio Guzman from King Juan Carlos University in Spain. It concerns an important topic of load balancing in cluster systems, namely adaptativity of the load balancing algorithms to changes of the workload in the system. Adequate accounting for additional load in the hosting system is of great relevance for correct optimization effects. The paper presents a thorough formal analysis of the workload variability metrics and their influence on the quality of load balancing algorithms. Four basic activities appearing in load balancing algorithms are identified, and based on them some algorithmic solutions are proposed to correctly deal with workload variability in system load balancing. The problem of dynamic load balancing algorithms robustness has been discussed. Two different robustness metrics sensitive to the applied type of opimization: local task-oriented or a global one enable selecting task remote execution or migration as load balancing operations. The proposed approach is illustrated with experiments. The second paper ``Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems'' is by Abdoulaye Gamatie, Eric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser, from University of Lille and INRIA in France. The paper is concerned with a very advanced methodology of designing correct parallel embedded systems for intensive data-parallel computing. In their previous research, the authors of the paper designed the GASPARD embedded system design framework. It is based on the hardware/software co-design approach through model-driven engineering. The framework is based on an UML-like model specification language in which hardware and software elements are modelled using a component approach with special mechanisms for repetitive structures. This paper tries to combine the modelling framework of GASPARD with the mechanisms of synchronous languages to achieve design verifiability provided for such languages. The paper shows how GASPARD models can be translated into synchronous models based on data flow equations in order to formally check their correctness. The proposed approach is illustrated with an example of a video processing system. The third paper ``Relations Between Several Parallel Computational Models'' is by Stephan Bruda and Yuanqiao Zhang from Bishop’s University in Canada. The paper is concerned with theoretical aspects of shared memory systems described by the parallel random access machine PRAM model and aims in studying performance properties of different types of PRAM systems. The attention is focussed on analysing the computational power of two more sophisticated PRAM models (Combining CRCW and Broadcast Selective Reduction), which include data reduction in case of concurrent writes. The paper shows that these two models have equivalent computational power, which is a new result comparing the existing literature. The performance of both models applied to reconfigurable multiple bus machines was studied as a possible architectural solution for current VLSI processor implementations. It was shown that in such systems under reasonable assumptions concurrent-write does not enhance performance comparing the exclusive-write model. Another result important for the VLSI technology is that the Combining CRCW PRAM model (in which data of concurrent writes are arthmetically or logically combined before write) and the exclusive-write on directed reconfigurable busses perform in equivalent way under strong real-time requirements. The fourth paper ``Experiences with Mesh-Like Computations Using Prediction Binary Trees'' is by Gennaro Cordasco, Biagio Cosenza, Rosario de Chiara, Ugo Erra and Vittorio Scarano from the University ``degli Studi'' of Salerno and the University ``degli Studi della Biasilicata'' of Potenza in Italy. The paper concerns optimization methods for mesh-like computations in clusters of processors. The computations are perfomed assuming a phase-like program execution control using a tiling approach which reduces inter-processor communication. A temporal coherence is also assumed, which means that task sizes provide similar execution times in consecutive phases. Temporary coherent computations are structured in a Prediction Binary Tree, in which leaves represent computing tiles to be mapped to processors. A phase-by-phase semi-static load balancing is introduced to the scheduling algorithm. The scheduling algorithm is equipped with a predictor, which estimates the computation time of next phase tiles based on previous execution times and modifies the tiles to achieve balanced execution in phases. For this, two heuristics are used to leverage on data locality in processors. The proposed approach is illustrated by the example of interactive rendering with Parallel Ray Tracing algorithm. The fifth paper ``The Influence of the IBM pSeries Servers Virtualization Mechanism on Dynamic Resource Allocation in AIX 5L'' is by Maciej Mlynski from ASpartner Limited in Poland. The paper concerns a very up-to-date problem of system virtualization and presents the results of research carried on IBM pSeries servers. IBM is strongly developing the virtualization technique especially on IBM pSeries servers enabling an improved and flexible sharing of system resources between applications. The paper investigates novel facilities for dynamic resource management such as micro-partitioning and partition load manager. They enable dynamic creation of workload logical partitions of system resources and their dynamic mangement. It includes run-time resource re-alocation between logical partitions including setting of sharing specifications as well as run-time adding/removing/setting parameters of resources in the system. It remains an open question how to properly tune parameters of the operating system using the provided virtualization facilities to obtain the best efficiency for a given application program. The paper presents the results of experiments which study the effects of tuning the disk subsystem parameters under the IBM AIX 5L operating system with the use of the provided virtualization facilities on the resulting application execution performance. The results show that even small deterioration in the resource pool status requires an immediate adaptation of the operating system parameters to maintain the required performance. The sixth paper ``HeteroPBLAS: A Set of Parallel Basic Linear Algebra Subprograms Optimized for Heterogeneous Computational Clusters'' is by Ravi Reddy, Alexey Lastovetsky and Pedro Alonso from University College Dublin in Ireland and Polytechnic University of Valencia in Spain. The paper concerns the methodology for parallelization of linear algebra computations for execution in heterogeneous cluster environments. The design of the HeteroPBLAS library (Parallel Basic Linear Algebra Subprograms) for heterogeneous computational clusters is presented. The main contribution of the paper is the automation of the parallelization and optimization of the PBLAS, which is done by means of a special user interface and the underlying set of functions. An important element is here a performance model that is based on program code instrumentation, which determines parameters of the application and the executive heterogeneous platform relevant for execution performance of parallel code. The parameter values specified for or returned by execution of the performance model functions are next used for generation and optimal mapping of the parallel code of the library subroutines. The proposed approach is illustrated by experimental results of execution of optimized HeteroPBLAS programs on homogeneous and heterogeneous computing clusters. Marek Tudruj

Distributed method invocations require dynamic scheduling algorithms and efficient resource projections to provide timeliness guarantees to application objects. In this paper, we present a dynamic scheduling algorithm that examines the computation times, real times and resource requirements of the application tasks to determine a feasible schedule for the method invocations. The schedule is driven by the laxities of the tasks and the importance that the tasks have to the system. Tasks span processor boundaries, and request messages carry scheduling parameters (laxity values) from one processor to another, yielding a system-wide scheduling algorithm that requires only local computations. Experimental results validate our scheduling algorithm, and show that it has minimal overhead.

Despite distributed in computation and data storage, current data-parallel computing systems are centralized in task scheduling, which results in hierarchies that create single point of failure, limit scalability, and increase administration costs. In this paper, we propose a fully decentralized scheduling algorithm for data-parallel computing systems on peer-to-peer (P2P) networks. Our scheduling algorithm eliminates the centralized scheduler by letting each node in the network make scheduling decisions. To achieve good performance, data locality, which stresses the efficiency of colocating tasks with their input data, and load-balancing, should be considered jointly, and in a decentralized fashion. By exploring a backpressure-based approach, the proposed task scheduling algorithm strikes the right balance between data locality and load-balancing with each node only knowing the status information of part of the nodes in the network, and proves to maximize the throughput.

RISC-V is a new and rapidly developing instruction set architecture, the main feature of which is its openness for the free use. For this reason, RISC-V is becoming more and more popular among companies with a wide range of specializations, both with hardware and software developers. The RISC-V architecture specification defines a set of standard extensions in addition to the basic instruction set architecture that can be useful in a variety of applications among which is the use in automation and process control systems in Electrical power engineering. One of the useful extensions is an extension for bit manipulation, whose instructions were originally invented by Intel and ARM in order to improve power consumption and performance. This work presents an implementation of the Zbb extension of basic bit manipulation in the Verilog language. The developed module is integrated into the schoolRISCV soft processor core. Its modeling and verification of correct operation were carried out using the ModelSim software. The processor was synthesized and prototyped on the Terasic DEI-SoC FPGA board. In addition, support for new instructions from the implemented extension was added to the assembler. Runtime simulator RARS was used also. The analysis of the performance of the extended core showed an average acceleration of the program execution by 29.9%; the amount of memory occupied was reduced by 37.5%. The increase in performance was achieved due to the consumption of a larger number of logic elements and registers.