Finite buffer analysis of multistage interconnection networks

Studies issues of multicasting in multistage interconnection networks (MINs) for large-scale multicomputers. In addition to point-to-point communication among the processing nodes, efficient collective communication is critical to the performance of multicomputers. This paper presents a new approach to support multicast communication, on the basis of a restricted address encoding scheme which constructs a short fixed-size multicast header, and a recursive scheme that recycles a multicast packet one or more times through the network to send it to the desire destination nodes. We propose a novel deadlock-free multicast algorithm for multiple multicast packets in MIN-based multicomputers. We also present a performance model for the unbuffered MIN using the multicast algorithm and analyze its performance in terms of the network throughput, where several multicast communications are considered.

Performance analysis of multistage interconnection networks with redundant links

Banyan Networks are a major class of Multistage Interconnection Networks (MINs). They have been widely used as efficient interconnection structures for parallel computer systems, as well as switching nodes for high-speed communication networks. Their performance is mainly determined by their communication throughput and their mean packet delay. In this paper we use a performance estimation model that is based on a universal performance factor, which includes the importance aspect of each of the above individual performance factors (throughput and delay) in the design process of a MIN. The model can also uniformly be applied to several representative networks. The complexity of the model requires to be investigated by time-consuming simulations. In this paper we study a typical (8X8) Baseline Banyan Switch that consists of (2X2) Switching Elements (SEs). The objective of this simulation is to determine the optimal buffer size for the MIN stages under different conditions

Self-routing algorithms for strongly regular multistage interconnection networks

Extended generalized shuffle (EGS) networks1 have recently been proposed as a broad class of multistage interconnection networks (MINs) that include strictly non-blocking networks as well as networks with finite blocking probabilities. These networks can be viewed as extensions to generalized shuffle networks2 (GSNs) that include the facility to fan-out and fan-in at the input and output stages, respectively, of the interconnection network. We present a new class of packets-witched EGS networks. At the heart of these networks is a unipath EGS network that allows a continuous tradeoff between a crossbar and a traditional MIN in terms of fan-out and fan-in versus number of stages. We show how switching networks with self-routing capability and arbitrarily low packet contention rates can be achieved by replicating the unipath network. We also compare the performance and cost of such networks with those of the GSN. Finally, we discuss the utility of these new packet-switched networks for photonic switching using smart pixels.

Delta networks are a class of multistage interconnection networks with gate complexity less than crossbar switches that are easy to control, and which include several networks that have been proposed in the literature as special cases. Buffered delta networks have queues of packets between the stages of the network. This paper presents analytic and simulation results for the performance of delta networks in a packet communication environment. The performance of buffered delta networks is compared with unbuffered delta networks and crossbar switches. It is demonstrated that buffering produces considerable improvement in the performance of these networks, making their performance comparable to that of crossbar switches.

On fault diagnosis of multistage networks with four valid states

Consider a discrete time queue with i.i.d. arrivals (see the generalisation below) and a single server with a buffer length m. Let {T}_{m} be the first time an overflow occurs. We obtain asymptotic rate of growth of moments and distributions of {T}_{m} as m \to \infty. We also show that under general conditions, the overflow epochs converge to a compound Poisson process. Furthermore, we show that the results for the overflow epochs are qualitatively as well as quantitatively different from the excursion process of an infinite buffer queue studied in continuous time in the literature. Asymptotic results for several other characteristics of the loss process are also studied, e.g., exponential decay of the probability of no loss (for a fixed buffer length) in time [0, n], as n \to \infty, total number of packets lost in [0, n], maximum run of loss states in [0, n]. We also study tails of stationary distributions. All results extend to the multiserver case and most to a Markov modulated arrival process.

Adaptive clocking (AC) has shown promising results for digital systems when there is a supply droop. However, coping with clock buffer delay and coarsely quantized clock frequency still remains a challenge. To solve these issues, we propose a supply tracking clock modulator placed after the clock buffer, which continuously changes the clock frequency to the supply. A prototype fabricated in 28-nm CMOS allows 36% higher system clock frequency and 25% higher power efficiency in a 15% supply droop, than a normal system without AC.

Performance analysis of synchronous multibuffered packet-switching networks

The queueing analysis of store and forward data communication networks is complicated by the fact that messages preserve their length as they traverse the system: in the queueing model service times of a message at successive queues (channels) are dependent. The present study considers the case of two communication channels in series with identical capacities and with a finite intermediate buffer. That part of a message for which there is no room in the buffer is lost. The resulting queueing model of two queues in series with identical service requirements at both queues is extensively analysed. Results include the distribution of the response time in the second queue (time in buffer plus transmission time in second channel) and of the total amount of work in the second queue. A comparison is made with the analogous queueing model with independent service requirements.

A low-power multi-phase clock 20Gb/s 1:4 Demultiplexer (DEMUX) without inductors is designed in 0.18μm Complementary metal oxide semiconductor (CMOS) process. The 1:4 DEMUX includes two 1:2 DEMUX cells, one 1/2 frequency divider cell, some data and clock buffers. A dynamic CMOS logic latch is used in the 1:2 DEMUX cell and a single clock dynamic-loading latch is used in the 1/2 frequency divider cell. These two kinds of logical structures not only reduce power dissipation and area, but also have an output rail-to-rail level. The rail-to-rail level can offer high noise margin and implement seamless connection without logic level conversion in system integration. The test results show that when the data rate of the input pseudorandom is 20Gb/s and the sequence length is 231-1, this 1:4 DEMUX can work well at a supply voltage of 2V. The output swing is 450mV with external 50 Ohm load and the die size is 0.475×0.475 mm2. The chip power dissipation is 86mW, when four pads connect with a four-channel oscillograph.

Because of their ability of nonblocking and fault tolerance, multistage-multipath networks provide useful characteristics for ATM switches and large-scale parallel computers. In this paper an analytical model for the analysis of ATM switches based on multistage-multipath packet switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed model is general in that it analyzes ATM switches under uniform and nonuniform traffic. First, a general model of synchronous buffered switching element, using output buffering, under an assumption of finite buffer size for a very general class of traffic patterns, is presented. It is assumed that the subsequent stages of the network are nearly independent, and a model is extended for the entire network under this assumption. The analytical results obtained with the proposed model are then compared with the results obtained for single path networks, and it is shown that the model is general enough for the class of multipath networks.

Analysis of Packet Switching Communication Networks with Finite Buffers

: We have encountered no obstacles to our research and have in fact made excellent progress toward our stated goals. In particular with respect to fast-packet switching using multistage interconnection networks, we have indeed carried out the analysis of finite and infinite buffered networks with arbitrary traffic patterns and a variety of internal operating procedures. In the area of lightwave networks, we have carried out the evaluation of wavelength division multiplexing for local area networks and for passive star topologies. In the area of Boolean n-cube interconnection networks, we have studied routing in such networks under stable conditions with finite buffers (the typical case) and then further extended these studies to deal with the case of unreliable nodes, thereby providing a fault tolerant routing procedure. In the area of distributed simulation we have carried out extensive analyses of the behavior of time warp systems for the two processor case; these are exact results and have led the way for considerable research in this area.