Finite state machine partitioning for low power

In this work, an efficient technique of clock and power gating is concurrently introduced in finite state machines (FSM) with a view to minimising the overall power dissipation. The proposed power gating concept works on the principle of shutting down the power supply to the FSM during periods of inactivity. The extraction of the inactivity criteria is based on the occurrence of self-loops within the FSM or an unchanged FSM output between successive clock pulses. Clock gating, on the other hand, disables the clock signal to the sequential blocks of the FSM during this inactive/idle periods. The idea of implementing the gating in both the state logic as well as output logic is introduced in this work. The proposed approach has been introduced in three benchmark FSM circuits, simulated and synthesised in Cadence digital design tool. The results indicate a maximum of 73% total power savings (dynamic and static) with an average penalty of 27% area (approx.).

New algorithms of coding the internal states of finite-state machine (FSM) have been (were) proposed. These algorithms make it possible to reduce the power consumption of sequential devices at the stage of their designing. The algorithms presented are based on solving the minimization problem of the switching activity of FSM memory elements that directly results in the reduced power consumption. The sequential and iterative algorithms of coding the FSM internal states have been proposed that are focused on the input power reduction. The experimental studies corroborated a substantial reduction of the power consumption in devices designed with the use of the described algorithms of coding as compared with the known approaches.

A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.

The finite state machine (FSM) needed for the low power system pulse frequency modulated (PFM) mode in a buck converter is usually asynchronous because the fast clock needed for a synchronous FSM consumes too much power, or is maybe even not available. However, the implementation, verification and testing of a asynchronous FSM is complicated compared to an synchronous one. This paper presents a concept of a semi-synchronous FSM that combines the benefits of both synchronous and asynchronous state machines. The result is a FSM which runs at high clock frequency, consumes very little power and can be implemented, verified and tested as a synchronous FSM. This concept has been used to design a PFM FSM in a field programmable gate array (FPGA) and in a 65 nm CMOS technology.

Finite state machines (FSMs) control the functionality of System-on-Chip (SoC) designs. The security and trustworthiness of SoCs can be compromised by exploring the vulnerabilities of their FSMs. Any deviation from the specification of FSMs can endanger the security and trustworthiness of SoCs. This is a critical concern when an FSM is responsible for controlling the usage or propagation of protected information (e.g., secret keys) in a secure component. FSM vulnerabilities may be introduced by a rogue designer or an attacker who inserts hardware Trojans in the FSM implementation. Traditional FSM design flows as well as CAD tools may create unintentional security vulnerabilities in FSM designs (e.g., when a synthesis tool is trying to optimize a gate-level netlist). These vulnerabilities can also be introduced unintentionally by a CAD tool. In this chapter, we present an efficient formal analysis framework based on symbolic algebra to find FSM vulnerabilities. The proposed method tries to find inconsistencies between the specification and FSM implementation through manipulation of respective polynomials. Security properties (such as a safe transition to a protected state) are derived using specification polynomials and verified against implementation polynomials. In case of a failure, the vulnerability is reported. While existing methods can verify legal transitions, the proposed approach tries to solve the important and non-trivial problem of detecting illegal accesses to the design states (e.g., protected states).

A new fast PWM modulation strategy for power electric converter based on finite set state machine theory

A popular approach to reduce power consumption is to identify self-loops in a state transition graph (STG) of a finite state machine (FSM) followed by gating the clock with a suitable function to power down the circuit (implementation of the FSM) during the self-loop cycles. Although this approach is effective in circuits with plenty of self-loops, it fails for FSMs without self-loops. Since self loops may not be inherently present in a given FSM, we decompose it into interacting FSMs such that they have plenty of self-loops. In this paper we present a novel partitioning algorithm to decompose a given finite state machine. By using this approach, we could save upto 71% of the total power on circuits like fetch, where other techniques could not save any power.

Current industry design tools and design flow are developed to improve system performance in terms of speed, size, and power consumption. With security and trust becoming more important for system design, how much can we trust the systems built by these tools? In this chapter, we first give motivational examples to show the potential trust vulnerabilities. Then we focus our investigation on sequential system design from the perspective of finite state machine (FSM). We define the notion of trusted FSM both in the most general sense and specifically when state reachability is used as the trust metric. We give a set of necessary and sufficient conditions to build trusted systems in both cases. More specifically, we find that the traditional FSM synthesis procedure will introduce trust vulnerabilities and cannot guarantee any the logic implementation of the FSM to be trusted. Indeed, we show that not only there exist simple and effective ways to attack a sequential system, it is also possible to insert hardware Trojan into the design without introducing any significant design overhead. We then propose a novel practical approach to designing trusted circuits from the FSM specification. We demonstrate both our findings on the security threats and the effectiveness of our proposed method on the MCNC sequential circuit benchmarks.

(Self-)reconfigurable finite state machine (FSM) had been introduced as a formal model to implement the sequential circuit which can be reconfigured during the operation. The reconfiguration is initiated by the external events or by the controller that generates the reconfiguration transitions. In this paper, we optimize the number of reconfiguration transitions required to reconfigure a given FSM into a new target FSM. A serious limitation of previously proposed techniques is that they depend on the number of essential transitions which are the different transitions between a given and a target FSMs. In this paper, we propose a new technique based on FSM decomposition to decompose a given and target FSMs into two sub machines. A part of essential transitions is implemented as a single decomposed submachine with the same functionality in two decomposed FSMs. This submachine is inactive and has no effect in the normal operation but reduces the number of essential transitions during the reconfiguration. We give a decomposition strategy, realize the proper hardware, and provide a set of experimental results that shows the reconfiguration transitions can be substantially reduced, in some cases up to 54%

In this paper we outline a theory for the environment-modeling problem , the problem of abstracting component finite state machines (FSMs)bordering a particular FSM of interest within a network of interacting FSMs. The goal is to lay a theoretical foundation for the automatic state reduction of large FSM networks. We feel this is a prerequisite for the efficient use of many verification techniques. We focus on computing conditions for the safe removal of a component FSM in a FSM network, where removal is safe if it preserves a certain well-defined trace equivalence. We present an optimized algorithm for determining language universality of a FSM, as well as determining independence of a FSM from those of its inputs connected to outputs of neighboring FSMs. These two properties, input independence and language universality, provide the necessary and sufficient conditions for safe removal. In addition, we show how simulation relations can be utilized, both to reduce the cost of computing safe removal and to create an appropriate abstract FSM when safe removal is not possible.

Verification and test are critical phases in the development of any hardware or software system. This article focuses on black box testing of the control part of hardware and software systems. Black box testing involves specification, test generation, and fault coverage. Finite state machines (FSMs) are commonly used for specifying controllers. FSMs may have shortcomings in modeling complex systems. With the introduction of X-machines, complex systems can be modeled at higher levels of abstraction. An X-machine can be converted into an FSM while preserving the level of abstraction. The fault coverage of a test sequence for an FSM specification provides a confidence level. We propose a fault coverage metric for an FSM specification based on the transition fault model, and using this metric, we derive the coverage of a test sequence. The article also presents a method which generates short test sequences that meet a specific coverage level and then extends this metric to determine the coverage of a test sequence for an FSM driven by an FSM network. We applied our FSM verification technique to a real-life FSM, namely, the fibre channel arbitrated loop port state machine, used in the field of storage area networks.

A heuristic method for encoding internal states (state assignment) of finite state machines (FSMs) so as to reduce their power consumption is proposed. A feature of the proposed approach is that the state assignment procedure takes into account the activity function of the memory elements when the FSM transits from a current state to other states that have already been encoded. A procedure for determining the power consumption of the FSM based on the codes of its internal states and probabilities of appearance of units at each input of the FSM is described. Experiments showed that the proposed approach makes it possible to reduce the power consumption of the FSM by 39% on the average compared with the NOVA algorithm and sometimes by 68%. In conclusion, the possibilities of improving the performance of the proposed algorithm in the synthesis of a specific FSM are discussed and promising directions of further research are indicated.

Switching activity and capacitive load both affect power consumption in VLSI circuits. In two-level logic implementations, due to the regular structure, more information about the find implementation is available at an early stage. In order to optimize power during the state encoding step in the synthesis of finite state machines (FSMs), both capacitance and switching activity need to be considered. Most of the previous work does not consider accurate measures of both capacitance and switching activity on all nodes in the circuit simultaneously. We propose a new approach based on the concept of dichotomy, to find accurate measures for both switching activity and capacitive load on all nodes in two-level implementations of FSMs from their symbolic specification. The area of the resulting implementation can also be measured in the proposed model. Experimental results on MCNC benchmarks indicate the effectiveness of our approach in reducing the power consumption. The areas of the resulting implementations are also reduced in almost all the cases, indicating that power and area are strongly related in two-level implementations.

This paper obtains upper and lower bounds for the switching activity on the state lines of a finite state machine (FSM) that is driven with typical input sequences. By exploiting the symmetries between the Hamming distances of state encodings, we obtain tight bounds on the average Hamming distance, which is proportional to the average switching activity and the overall power dissipation of the system. Since these bounds are independent of the state assignment and the actual circuit implementation, they can be used at an early stage of the FSM design to indicate the largest/smallest possible power consumption. The paper also discusses how redundant state encodings can be chosen to decrease power consumption.

This paper presents an intelligent control system of a miniature climbing robot to achieve precise motion control, minimize power consumption, and produce versatile behaviors. The gravitational effects degrade the motion control performance and are difficult to compensate exactly, especially in the case of the climbing robot. A fuzzy logic based control scheme is developed which is capable of compensating the gravity at different robot configurations and task conditions. In order to reduce power consumption, an optimal control law is developed which minimizes the energy used to vacuum the suction foot. Primitive behaviors are implemented to provide the robot with basic competence. A finite state machine (FSM) is developed to synthesize signals from multiple sensors, keep track of robot motion status, and schedule motion sequences. FSM is an effective computational method in behavior-based control paradigm to implement robot behaviors. Experimental results prove the validity of the proposed methods.