Flux Materials for Increased Yield of Package on Package Devices

As mobile and other electronic devices become smaller with more sophisticated functions the assembly technologies for compact and high-density packages have advanced dramatically. Recently Package on Package (PoP) technology has increased in use in the industry. In the conventional PoP manufacturing process, the solder bumps of the top package are immersed into a layer of tacky flux. Once the flux immersion is completed, the top package is placed on to the bottom package and soldered together. One of the challenges of PoP manufacturing is component warpage during the reflow process which had led to the incomplete merger of the solder bump from the top package with the solder land on the bottom package. Once the solder bumps of the top PoP component separate from the land of the bottom component, even if they come into contact again, the tacky flux activity is reduced leading to incomplete merger. The work focused on the development of solder paste rather than tacky flux for PoP manufacturing to reduce the incomplete merger occurring during soldering. The solder paste would have the benefit of reducing the gap between the land and solder bumps caused by component warpage, and would hold the two together more when molten to prevent incomplete merger. Tests were conducted on lead-free PoP solder pastes with adjustments in the flux thixotropic agents, activators and solvents in addition to the actual flux content used in the solder paste. The results of the investigations are presented.

In the last half a century, the complexity of electronic systems has undergone a sustainable rapid development stage following the Moore's law: the density of integrated circuits (ICs) was doubled every two years. As a result, electronic devices become more miniaturized in space and contain more power in unit volume. Electronic package has to deal with highly increased I/Os with fine soldering pitch. A symbol of the fast development of the package technology is using staked technique to develop three-dimensional (3D) package from 2D and 2.5D. The representative products are the package-on-package (PoP) technology in which packages are staked and through-silicon-via (TSV) technology in which chips are staked. The PoP has been widely used in handheld products such as cell phones and PDA. The harsh environment in service and high integration in composition have brought big challengers to the design and process of the package. PoP technology has attracted great attentions. The staked composition has largely reduced the length of connection lines between packages. It is also coupled with modules design concept in which different functions can be contained in different packages and thus results in a convenience for efficient production. In view of the advantages, PoP is favored by cell phones and other handheld products. A great deal of work has been done on the general issues. However, given the short life period, detailed studies on specific aspects and individual products have not been covered in full. These include such aspects as the effects of pad design, stencil design and soldering profile on the reliability of PoP systems. The issue for how to increase the pass rate of soldering satisfactory under extreme deformations has also not been seen by the authors in report. PoP has raised challengers to package design. As a staked system, interactions are intensified between packages: the deformation due to the difference of the coefficient of thermal expansions (CTE) will be accumulated and the heat cannot be dispersed through the surfaces between packages. Furthermore, the staked packages become difficult to bend following the PCB as performed by single thin package. All the above factors can deteriorate mechanical damage. So we will work on investigation of the manufacturability and reliability of a PoP system through an integration of modeling, testing and design modification. This includes (i) finite element analysis (FEA) of the PoP system to identify the critical regions and deformation; (ii) experimental test of the PoP system to validate the FEA results; (iii) evaluation of the impact of thermal deformation on the quality and reliability of solder joints to form guidance for detail designs of PoP systems. Agreed results have been achieved from our modeling and testing. The thermal damage to the PoP system has been realized. The effect of manufacturing details of pad, stencil and soldering on the reliability of PoP systems has been analyzed. A guide for design procedure has been offered. Through this integrated investigation, we have obtained a good understanding to the mechanical performance of PoP systems and found the way for how to design relevant details for enhanced reliability. This has practical reference to PoP design and testing. In this paper, we work on the parts of integration modeling: research on printed board's deformation. Finite element method is used to predict the deformation of printed board in different copper case, testing the PCB s deformation by use moire, and correcting finite element model, after we master PCB deformation, we could design PCB such as layout, routing, and wiring to pave the way for the production of POP. Subsequent work with experimental continue to be in a future paper published in succession.

The needs to integrate devices into portable products with smaller form factor and more functionality have fueled enormous growth of 3D packaging technology. The package-on-package (PoP) is one of the 3D packaging solutions, by which the packaging and assembly houses can achieve a lower cost, faster turn benefits and testing prior to assembly. PoP is a complicated system with multi-layered structure, which induces more manufacturability issues, such as stand-off height issue and top & bottom packages having different types of warpage. In order to reduce R&D cost, achieve fast time-to-market and address most of the manufacturability issues during the development of a new PoP, a design advisor for PoP manufacturing has been developed based on the design for manufacturability (DFM) methodology. The key components of this design advisor are the validated numerical models, comprehensive materials library, design guidelines of PoP packaging and novel finite element analysis (FEA) techniques. With the developed novel FEA techniques for curing process simulation and seamless packaging process simulation, complete numerical models for PoP manufacturing were developed and validated, which can simulate the whole PoP manufacturing processes. The design advisor is easy to use by selecting package geometries, material properties and process parameters. By running the envelope-based design advisor for normal package design or the FEA-based design advisor for special package design, the detailed analysis reports can be generated, including simulation results, design evaluations and recommendations to ensure the first-time success of package design. Therefore, the design advisor can help improve the yield of complex PoP manufacturing processes leading to higher quality and confidence of manufacturing processes, faster time-to-market and lower overall manufacturing cost.

As the July 1, 2006 Pb-free deadline approaches, many electronics assemblers are beginning to fathom the changes and process demands required. The two biggest material concerns involve solder paste and components. This document provides practical recommendations for evaluating Pb-free solder pastes and ensuring that the selected solder paste will deliver assembly yields comparable to, or better than, the incumbent Sn/Pb solder paste. Since it is commonly considered that a Pb-free process is more difficult to control (due to more constraints on the printing and reflow), the use of statistics becomes even more essential in the evaluation of solder pastes. Without proper statistical techniques, it is difficult to accurately assess and rank the performance of various solder paste candidates. Statistics allow the user to adequately characterize variation. There is variation in every process, but operational efficiencies decrease as the variation from the target result increases. Statistics reveal the differentiation between common cause variation, which is controllable and expected, and special cause variation, which is unnatural and not expected. The special cause variation is what typically would result in a defect in the SMT process. When considering a Pb-free solder paste evaluation, there are a couple of things that need to be defined to enable statistical analysis: Define the part of the process to be evaluated: The smaller and less complicated that the evaluation is, the easier it is to characterize and measure results. It is better to run several small experiments than try one large experiment that tries to characterize a large number of variables. An example would be to evaluate the print performance of the various Pb-free solder pastes. Define the factors to evaluate: In the stencil printing process, one factor is the different Pb-free solder pastes. Other factors include various print speeds, the length of time between prints (response to downtime), etc. Define the response variables: It is essential to know the product attributes that are of the greatest importance to the process. These are the variables that should be measured. In the stencil printing example, solder paste volume is most often studied and is considered the most crucial variable. Once the experimentation results are collected, the statistical analysis begins. When comparing Pb-free solder pastes, the best paste is the one that provides the process the greatest precision (most consistent results) as well as greatest accuracy (results closest to the targeted values) i .

SnZn alloys are an attractive economical consideration for use in lead free solder materials due to the lower cost and lower melting points relative to SnAgCu (SAC) alloys. However, SnZn solder materials are significantly different both chemically and metallurgically from conventional SAC based Pb-free solder materials. One consequence of this is that SnZn powder reacts strongly with solder paste flux mediums resulting in paste shelf life measured in hours rather than weeks. There are also some question marks on the long term reliability of SnZn solder joints. These factors have previously prevented the development of a fully viable solder paste and soldering process. However, attempts to overcome these drawbacks by novel developments in fluxing technology have been performed. The characteristics and performance of a model SnZn solder paste including viscosity, solderability, reflow performance on Pb-free printed wiring boards (PWBs), viscosity and shelf life have been compared with standard SAC solder pastes in a surface mount assembly process. In addition the long term reliability of SnZn solder joints under accelerated temperature cycling (ATC), 0°C-100°C, has been assessed. The results show that significant increases in shelf life can be achieved by developments in flux technology whilst also providing acceptable soldering performance and favourable long term reliability characteristics. These encouraging observations with SnZn alloys in solder pastes may potentially lead to a viable lower cost alternative to conventional SAC solder pastes.

The continued demand for higher level of integration has led to the industry's adoption of 3D packaging technologies and, in particular, the Package-On-Package (PoP) configurations. This technology allows for vertical integration of the memory package and the logic package into one stacked package. The top package is primarily a memory module including some combination of Flash and SDRAM, while the bottom package typically contains the logic die, which is a baseband or an application processor of some kind. Top and bottom package are connected via the pads that are located on the top side of the bottom PoP package, and these pads are used to connect the top PoP (memory module) Ball Grid Array (BGA) solder balls to the bottom PoP package. This paper details the various PoP package types including bare-die PoP, Embedded Solder On Pad (eSOP) PoP, and Laser-Via PoP that have proliferated to meet the increasing market demand. Also, the various package types are compared to each other in terms of their feasibility for adoption in the next generation PoP with tighter pitch and lower package profile.

The increasing demand for portable electronics continues to be a dominant factor for technological advancements in the development of fine pitch devices. Assembling these highly compact and high Input/Output (I/O) density devices efficiently on Printed Circuit Board (PCB) assemblies can be a challenging task. Extensive literature is available focusing on stencil printing challenges and reliability studies of fine pitch devices. However, for 0.40 mm pitch Ball Grid Array (BGA) components, the effect of key factors like pad design of the PCB (Solder Mask Defined – SMD and Non-Solder Mask Defined - NSMD), solder paste type, and stencil technology on the stencil printing process requires further research. Also, the solder paste print definition for fine pitch printing greatly depends on the capabilities of the stencil printer and on printing process parameters. In this paper, the effect of PCB pad design (SMD/NSMD), and solder paste type (Type 3/Type 4) have been studied and discussed. Additionally, the performances of three different stencil printers were studied to determine their effect on the solder paste volume and print definition. Automated Solder Paste Inspection (SPI) was used to measure the print quality in terms of print volume, print height as well as printing defects such as solder bridging. Based on the results, the volume of solder paste deposited was higher in the case of NSMD pads as compared to SMD pads. Both type 3 and type 4 solder pastes were found to be compatible for the assembly of a 0.40 mm pitch BGA. It was also observed that the printing process and print quality were more dependent on the stencil printer used in the case of the 0.40 mm pitch components as compared to coarser pitch components, such as 0.50 or 0.80 mm pitch devices.

Despite the tackiness offered by ball attach fluxes, they have failed to prevent ball movement on Solder on Pad (SoP) finishes when the solder protrudes above the solder mask. Dippable solder paste provides the tackiness needed for these adverse situations as well as small solder particles that inhibit ball rolling due to mechanical or convective forces downstream. Also, other pad finishes like OSP has issues with oxidation with partial pad wetting as a common defect. The use of dippable paste has also demonstrated relief with these wetting related issues. The most current application of dippable pastes is in the assembly of stacked BGA's also known as Package on Package (PoP). Although water clean formulations are typical in BGA assembly, PoP assembly typically utilizes no clean formulations. Although tacky flux has been successful in many PoP applications, issues such as coplanarity and package tolerances that require increasing the sphere size during assembly have found benefit from dippable solder paste.

The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in-pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.

0201 assembly plays a very important role in the continuing miniaturization of electronics products. After a systematic study using Sn‐Pb solder paste on pad design, machine evaluation, component qualification, and process optimisation, this study focused on the PCB assembly process for 0201 packages using Sn‐Ag‐Cu solder paste. The post‐reflow solder defects for a range of different spacings were examined for the different solder pastes.

PoP, Package-on-Package, becomes more and more popular in IC packaging industry because it provides a practical solution to reduce the footprint and enables separate package test before stacking them. It is widely accepted at mobile devices, especially for logic (bottom) plus memory (top) application. Meanwhile there are several technical challenges such as top to bottom package connection problem caused by warpage, fine pitch package stack issue due to bottom package mold height and worse thermal performance than that of a single stacked package. While many studies have been conducted on warpage and new type PoP for fine pitch interconnection, there is few existing study on the thermal performance of PoP. This paper investigates thermal characteristic of PoP, especially on the thermal interactions between bottom and top packages. CFD models are established to study such interactions. It is found that bottom package usually with a higher power logic die inside has great impact on the thermal budget of top package, which is usually a stacked memory package. Normal JEDEC junction to air (thetasja) or junction to board (thetasjb) thermal resistance cannot clearly describe the PoP thermal performance since the heat distribution between top and bottom package will greatly affect the results. A thermal resistance network is proposed to better represent the performance and can also give a quick estimation of junction temperature for simple calculation. The present paper then uses some fixed power of bottom and top package to evaluate different options of improving the thermal performance.

[Background and Motivation] System in Package (SiP) is pulling the evolution of technology instead of deep submicron of LSI. SiP assists coming AI/IoT/5G world. SiP has many implementation variations. When we examine the chip and package implementation technique for the target product, it's important task to find the optimal solution for the product considering trade-off between cost and performance. Compared with mass production products, it's important to optimize costs especially for small volume production products. Moreover, in terms of performance, compared to conventional packages, for high frequency products and SiP, since the margin becomes small and confirming system level electrical characteristics are necessary, in addition to conventional conceptual design and detail design, prototyping design is required to test its electrical characteristics while keeping lower cost. [Technical callenge] To do prototyping design at the early stage of product and find the optimum solution of the product, we created short turn-around time(TAT) iteration environment and distributed prototyping design. Quick Prototyping, which is a short TAT iteration environment, is based on the LSI/Package/PCB integrated co-design environment, estimates the chip size from the signal number of product, performs LSI design prototyping, using package automatic net assignment and the substrate auto routing, proceeds package prototype design and then confirms electrical characteristics. In the above, itfs possible to consider multiple implementation variations. In the distribution of prototype design, we utilize the LPB format (IEC 63055/IEEE 2401), have eliminated the interface(I/F) barriers between companies and tools, and have developed an environment for design prototypes and checking their characteristics throughout the industry. [Results and Conclusions] In collaboration with Semiconductor vendor Socionext Inc., as the above benchmark, 3D Flip Chip-Chip Scale Package(FCCSP) (with memory package with Package on Package(PoP) method) and 3D Fan-Out Wafer Level Package(FOWLP) (similarly in PoP method) as samples, the prototype design was created out. By comparison of the electrical characteristics, the Self Inductance of the FOWLP becomes half or less than FCCSP, the power supply noise could be suppressed. The shielding effect of FOWLP reduced the influence of crosstalk. We confirmed that FOWLP has advantage of electrical characteristics. On the cost side, in the LSI implementation of the FOWLP side, only the function blocks requiring performance were replaced with the fine node by chip partitioning, we examined to suppress the increase in cost while maintaining the performance advantage of FOWLP. With Quick Prototyping, cost and performance balance can be examined in the product review early stages, also by utilizing the LPB format for Quick Prototyping, from the negotiation stage with business partners, we can share the design data, focus on tuning the product itself and improve the competitive SiP products.

With the removal of the freons as cleaning agents in the electronic industry, the no clean soldering processes have taken a prominent place. This is a feasibility study to prove that an SMT process with solder paste is possible with a truly no clean flux. The flux used here is not incorporated into the solder paste but it is rather supplied by the soldering furnace atmosphere in a gaseous form. Formic acid vapors have been used as a flux in close environments to perform soldering. First R.D. Deshmukh et al (1), used formic acid vapors as a flux media to do soldering in a closed environment. Others followed trying to use the formic acid vapors in open environments, S. M. Adams (2), or even in wave soldering (3). Gary Freedman, Digital Equipment Corporation (4), in a SMT open furnace. In parallel, Y. C. Lee and his students did a lot of work at Colorado University, characterizing the soldering process using formic acid vapors as a fluxing agent, defining and characterizing the parameters (partial pressure, formic acid concentration, temperature) (5). At Macom we had a project of building power flip chip transistors, in the microwave regime (2 to 12 GHz). The best way to match the circuit was to mount the transistor onto the substrate in a flip chip fashion.

This article proposes an approach to high volume Package-on-Package (PoP) assembly that leverages the existing electronics packaging technologies for flip chip assembly. Several challenges and considerations are discussed. Several articles [1,2,3] describe in detail the requirements as well as examples of this new package. This article will demonstrate how to stack and assemble these modules by using automated placement machines and options used for flip chip assembly. Some modifications are required to accommodate the larger ball size of the bottom CSP as well as the use of solder paste in addition to flux. Stacking requires more accuracy than standard SMT placement Some existing SMT assembly machines can be modified to accurately place stacked CSP’s at high speeds with the appropriate modifications. This approach can be very cost competitive. We will also review the design of some test vehicles that were built to further examine process and assembly issues.

Bond-Via-Array (BVA™) technology has been developed to address the high density interconnect requirements of the next generation of package-on-package (PoP) solutions. This technology, while utilizing conventional assembly processes and equipment, can provide more than 1000 interconnections between the memory and the logic packages when stacked in a PoP format within a standard PoP package footprint. The vertical interconnections are achieved by utilizing well established wire-bond equipment and processes. An array of free-standing wire-bonds is formed along the periphery of the logic package to form electrical connections to the topside memory package. In this paper, key assembly process steps including free standing vertical wire-bond formation, film assist molding and fine-pitch PoP stacking will be described along with the results from manufacturing and reliability studies conducted in cooperation with 3 rd party equipment vendors to validate HVM readiness.