Quick Prototyping Design for More than Moore era

New, emerging, and existing markets demand ever-smaller electronic devices that surpass the performance of their physically larger predecessors with thinner and smaller form factors and lighter, increased functionality with faster data transfer, without sacrificing battery lifetime and affordability. Fan out wafer level packaging (FOWLP) is fast becoming the new die and wafer level packaging technology of choice for the next generation of compact, high-performance electronic devices, fulfilling the above requirements with higher I/O interconnect density and packages with multi-layer redistribution lines (RDL) with finer line/space widths. The versatility of FOWLP technologies provides the ability to expand into 3D packaging architectures such as multi-chip, system-in-package (SiP) assembly, and package-on-package (PoP) configurations. Implementing a unified FOWLP design approach requires a significant expansion in communication between the IC design world, the package design world, and a new dimension, that of communication and interaction with the OSAT/Foundry that will fabricate and assemble the complete device. FOWLP, as with other emerging High Density Advanced Packages (HDAP), have unique and often restrictive/strict rules and guidelines, a hybrid combination of traditional ASIC and organic packaging worlds. This paper will explore best-practice approaches for embarking on FOWLP design, including how to leverage your Foundry or Outsourced Substrate Assembly and Test (OSAT) partner, and how to ensure your design is manufacturable the first time to avoid expensive and time-consuming changes.

Fan-out wafer level packaging (FOWLP) is one of the latest technologies to meet the requirements of high performance and thin form-factor, especially for mobile application processors. To achieve a simple path way and thinner package form, many outsourced semiconductor assembly and test (OSAT) suppliers and foundries provide FOWLP capabilities. Most solutions are limited to the bottom 2D package area with a package on package (PoP) stacking structure to communicate logic to memory or a peripheral chip beyond the 2D distribution area. This means that communication between heterogeneous chips has more power and signal loss by PoP interconnection to reach hetero-chip functions through bulk solder ball joints and printed circuit board (PCB) laminated routing with more coarse trace pattern than a fan-out (FO) redistribution layer (RDL pattern). To improve this situation, high performance heterogeneous integration has been simulated and successfully realized with the novel 3D Silicon Wafer Integrated Fan-out Technology (SWIFT®) prototype as chip stackable, ultra-thin, high flexibility FOWLP for the first ultimate 3D packaging. Also, this has been proven to be a highly flexible and cost-effective structure with a low-risk process flow, low package warpage, stable electrical performance, and good reliability performance. The form-factor of the 3D SWIFT design with various structure options is as much as 45% thinner than PoP technology.

Fan-out wafer level packaging (FO-WLP) has become prevalent in past two years as a package option with large number of pin count. As the result of early development, the single die packages with single-sided redistribution has reached the maturity to take off. While the early applications start to pay back the investment on the technology, the developments have shifted to more advanced packaging solutions with System-in-Package (SiP) and 3D applications. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPDs gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology. Rozalia/Ron ok move from 2.5/3D to Passive 1-4-12.

Packaging technologies such as fan out wafer level packaging (FOWLP) and embedded chip in substrate technologies have gained a lot of attention recently from OEMs, OSATS, technology developers, and technology integrators in the integrated circuit (IC) industry as schemes for continuing wafer level chip scale package (WLCSP). Both technologies are focused on incorporating ICs into their packaging platform and on taking advantage of current process recipes and infrastructure as much as possible. However, by virtue of the new process steps and technologies required to get to 3-D packaged materials, such as through silicon vias (TSVs), wafer thinning and handling processes and requirements for alternative dielectric materials, many opportunities have arisen. Expectations are that many devices that follow a flip chip ball grid array (FCBGA) flow or WLCSP will adopt an embedded technology strategy for future generations. FOWLP has several advantages, over FCBGA and WLCSP including potential for system in package (SIP) configurations and 3-D integration, the ability to overcome pad limitation issues, and shorter interconnections and so higher electrical performance. However, to gain these advantages, requirements for processing will change due to the significant demands imposed on the materials used as permanent dielectric layers and the photoresists used in the fabrication processes. Cleaning chemistry must be designed to remove challenging films such as photoresists and residues created during other process steps; yet preserve the exposed metals such as the bond pads and Cu redistribution lines, as well as the permanent dielectrics. Device reliability and performance is heavily dependent on the proper working of all these components. The focus of this paper is to identify a manufacturable and reliable process and process window for removal of positive photoresists and residues in formation of under bump metallization (UBM) and contact pads in wafer level packaging (WLP). Our objective is to discuss a proven process that has been successfully implemented into a manufacturing environment. It has improved robustness and reliability over past-used solutions due to decreased sensitivity to moisture contamination, a significant cause of defects in many device applications.

Fan-Out Wafer Level Packaging (FOWLP) is the most popular packaging and integration technology today. It has evolved from providing basic routing of the bare chip electrical Input/Output (I/Os) connection to a complex multi-functionality System-in-Package (SiP) integration platform. The FOWLP has the unique ability to embed the bare chip in the mold compound and provides the rerouting of either fanning-out or fanning-in of the electrical connection using the Redistribution Layer (RDL). This has helped to support the continuous shrink of the device technology nodes which requires higher electrical speed and higher density I/O connection to the main PCB board. In order to miniaturize the electrical circuit or module size, and improve the performance, multi chips are integrated on the same molded package. In this way, the interchip connections are made using the package RDL without going through the PCB. Depending on the applications, the chips can be integrated laterally or stack vertically to achieve the shortest interconnect length or smallest package size. Besides the multi-chip integration, the mold compound of the FOWLP can also be used to realize RF circuits such as high Q inductor and high frequency antenna.

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed. ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning. Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.

The limitation of the package height in the smartphone becomes severer and severer. Especially in the case of application processer, TSV structure is necessary to clear 1mm package height that is stacked by 2-4 DRAMs inside. But not only the cost of fabricating Through Si Via (TSV) on the Si device is expensive, also handling of the thin chip is fragile. To solve these problems, we have developed ultra thin fan-out type wafer level package (UT-FOWLP) whose thickness is less than 100um. Using this WLP as Package-on-Package (PoP) stacked on System on a Chip (SOC), the total package height of application processor becomes thinner.

Heterogeneous integration for system in package (SiP), flip-chip integration in 3D packaging and embedded ICs in advanced Printed Circuit Boards (PCB) are all pushing the limits for low profile packaging. Advanced polymer materials applied in Semiconductor-on-Polymer™ wafer level chip scale packaging (SoP WLCSP) are gaining traction as a high reliability ultra-thin packaging solution. The 2019 roadmap for Heterogeneous Integration defines heterogeneous Integration (HI) as the integration of separately manufactured components into a higher-level assembly that provides enhanced functionality and improved operating characteristics. The development of this technology is a significant industry challenge that can evolve quickly with the application of SoP polymer based packaging. At advanced nodes, die yield falls exponentially with die size. Splitting a large monolithic SoC into smaller tightly coupled die, is an attractive alternative considering that die cost per unit area is escalating. The smartphone industry has been an early adopter of HI technologies in the use of SiP for multiple generations, essentially for the advantages in miniaturization, modularity for co-design, and enhanced generation-over-generation performance. The application processor is almost always on the most advanced node and housed in a Package on Package (PoP) configuration with memory component(s) stacked on top of this ASIC. Teardowns of the Package-on-Package (PoP) packages for Apple XSMax, Samsung Galaxy S9+, and Huawei 20 Pro have shown the utilization and need for continued z-axis thickness scaling. Implementation of SoP CSP for package in package integration or for chip on thin PCB, interposer or flex can provide another package capability for evolution of multi-layer heterogeneous integration. Reliable ultra-thin polymerized die have the potential to tackle the third dimension (z-axis) of total IC package volume in 3D integration. SoP die can replace current full thickness or partially thinned (typically >250µm) die with <35µm package thickness devices. In addition, the SoP process has the potential to extend package roadmaps enabling smaller higher performance packages in several areas, including Fan-Out (FO). Thin bridge die could simplify localized high IO for substrates. Thin embedded IPD (integrated passive devices) have the potential to increase the capability and shrink the size of substrate process based passives, similar to the performance increase for wafer based devices versus printed electronics. In addition thin high IO die could allow simplified embedding in substrates. The differentiation of PCBs, interposers and flex circuits is starting to blur. Package integration within the layers of these devices can create embedded ICs that take less system space and improve system performance. Traditionally, manufacturing steps to place an IC within the board substrate vary and require space to be created for the component body, in the form of a cavity for traditional packaged ICs. In Integrated module board (IMB), components are aligned and placed inside a cavity that is routed to the core laminate by controlled-depth routing. The cavity is filled with molding polymer to ensure chemical, mechanical, and electrical compatibility with the substrate. Isotropic solder is impregnated with the polymer to form reliable solder joints when the embedded part is laminated into the stack. Polymerized ICs in SoP CSP eliminate cavity requirements and molding polymers for IMB. Chip in polymer (CIP) approaches use thin chips in built up dielectric layers of PCBs, rather than integrating them into the core layers. When SoP CSP is applied, it is feasible to achieve the same capability, but with a much smaller z-axis and without creating a surface geography perturbation. This presentation will include an introduction to SoP CSP utilizing advanced polymer technology for accelerating evolution of HI, PoP and Embedded applications.

The development of Low-Density Fan-Out (LDFO), formerly Wafer Level Fan-Out (WLFO), platforms to encompass the requirements of potential new markets and applications such as the Internet of Things (IoT) is crucial to maintain LDFO as the leading Fan-Out technology. This drives the development of a new set of capabilities in the current standard LDFO process flow to break through the existing technology boundaries. One of the most widely discussed advantages of LDFO packaging is heterogeneous high-density system integration in a package. LDFO System in Package (LDFO SiP) integrates active dies, passive components and even already-packaged components using other packaging technologies. This heterogeneous integration is based on a wide range of different geometries and materials placed inside the LDFOSiP with high accuracy. Ultimately, heterogeneous integration will be fundamental to achieve new levels of miniaturization. However, multi-die solutions face several challenges such as bare-die availability, passives integration, antenna integration, low power budget, test complexity and reliability. Package research and development (R &D) must overcome all of these issues to build a product with high volume manufacturability. The wafer level SiP (WLSiP) technology required to enable the new features and processes needs to be ready for high volume manufacturing of new products at high yield and reasonable cost. This paper presents the approaches used to effectively enable LDFO SiPs (WLSiPs): 1. A pre-formed vias solution is employed to connect front to back side of the package, including development for high accuracy via bar placement. 2. A wafer front-side to back-side redistribution layer (RDL) alignment solution was developed. 3. Space requirement reduction between components to achieve the smallest possible package. 4. Miniaturized Bluetooth antenna integration in the RDL. 5. Creation of a stacking concept (vertical connections to create a modular system that enables easy addition of new features to the final product).Inside the package (excluding the area reserved for the antenna), components are densely packed: several sensors, power management components, radio communication and all required passives are incorporated into a single WLSiP. Connecting all these features to create a component that works by connecting only a single battery required implementing a double sided, multi-layer RDL, while maintaining the ability to create a 3D solution by stacking vertical connections for several other solutions. The result is an approach that easily adapts the system to a variety of customers' needs. The work done is part of the collaborative COMPETE2020-PT2020 funding program under “IoTiP-Internet of Thing in Package” project n°017763, Projetos de I &DT Empresas em CoPromoção. LDFO, LDFO SiP, Fan-Out WLP, WLSiP, SiP, Multi-Chip-Package, Antenna-in-Package, Package-on-Package, Through Mold Via, TMV®, TPV.

The increase in the number of handheld electronics devices and increased functionality in these same devices are significant drivers in innovative packaging designs. One of the newer package types to be introduced into the market place to meet these demands are the package on package (PoP) devices. While packaging houses have been stacking die within memory and other packages for several years, this methodology is subject to known good die issues and other challenges that can drive up cost. In addition, this limits the designer on what functionality can be “stacked” since these come packaged together in a single unit from the same supplier. Stacking packages offers significant advantages from a design standpoint. As long as the pad designs are compatible, different device types can be stacked allowing for more versatility in the design and the assembly. On the other hand, assembling these devices on a standard SMT line can present challenges. Some assemblers purchase or acquire these devices pre-assembled, but the trend is towards assembling these on the PWB during a standard SMT process. Once solder paste is printed on the PWB and the first level component is placed, the attachment methodology of the second level device can be problematic. There are several proposed methods for the second level interconnect, two of the most common are flux and solder paste. In this paper, different flux materials used to assemble PoP devices are compared. The impact of various flux formulations on aspects of the PoP SMT process is investigated. These include methods of delivering the flux to the package, inspection metrics/methodologies, reflow performance, and reliability. These various flux materials are also compared to solder paste materials variants designed for the PoP process.

Three-dimensional packaging (3DP) is an emerging trend in microelectronics development toward system in package (SiP). 3D flip chip stacking structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. Prototype design and fabrication of multi-stacked flip chip three dimensional packaging (3DP) with TSVs formed by deep reactive ions etching (DRIE) and TSVs plugging by copper plating for interconnection are studied and discussed in details. The three middle chips and top chip are stacked by a flip chip bonder and the solder balls are reflowed to form the 3DP structure. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented in this paper.

With the rapid development of IC technologies, topics of 3D stacked IC packages are now being studied vastly around the world. In 3D stacked IC technologies, many electrical characteristics have been proved to have great improvements, but their corresponding thermo-mechanical problems are raising as well. Due to the reason of ICs stacking, thermo-mechanical problems are becoming more serious than those in traditional single IC package. These problems include the heat dissipation, die breaking, interfacial delamination, via cracking and so on. These corresponding problems not only cause failures in 3D stacked IC packages but also have significant influences on reliability. For the sake of realizing critical stress distributions in 3D stacked IC packages, the three dimensional finite element analysis (FEA) modeling has been employed in this paper. The 3D-WLP (wafer-level-package) with ten layer chips stacking is selected as our test vehicle. By using three dimensional FEA modeling, thermal induced stress distributions in 3D-WLP when subjected to a uniform temperature change can be illustrated. Further, the design of experiments (DOE) analysis for design optimization has also been used to obtain the sensitivities of geometry and material properties of 3D-WLP. Several geometric dimensions and material properties are selected as main design factors and the average value of maximum von Mises stress in copper vias and chips is chosen as the response to be optimized. Through the DOE analysis, the optimum geometry and material properties of 3D-WLP and this result in smaller von Mises stresses in copper via and chip configurations can be obtained. These results can be most effectively used as design guidelines to engineers when optimum stress solutions in 3D-WLP are required.

With rapid development of modern society, the requirements for high precise temperature and humidity is growing rapidly, for example production, storage, transportation, environment etc., these all have strict requirements for temperature and humidity testing, so the real-time monitoring of temperature and humidity and alarm prompt is extremely important. In this paper, a temperature and humidity automatic alarm recorder is designed, which uses stm32 as control center, combines the technique of sensor technology, GSM technology and serial port to finish button control measurement of temperature and humidity or two road all the way. In the study, the system's hardware and software design are introduced in detail and testing results show that the system can realize the function of the temperature and humidity measurement record and alarm.

Outlines the principle of the Dutch auction, whereby the price begins at a high level and decreases by steps until a bid is made. Describes an integrated hardware and software system which uses Internet communications to enable remotely created bidders to participate in real‐time Dutch auctions and which meets the stringent requirement that synchrony be maintained among bidders’ terminals to ensure that each bidder has a fair chance to bid at the current offer price. Defines the principal functions of the system and characterizes its available resources. Illustrates implementation using a prototype design. Pays particular attention to bidder terminal synchronization, bidder authentication, and auction client security. Includes the possibility of a system variant using ISDN interconnect and PC‐based bidders’ terminals.

For portable and wearable devices, having good functionality and being lightweight are a must. To improve the functionality of the device, System-in-Package (SiP), Package-on-Package (PoP), Multi-Chip-Module (MCM), or Chip-on-Wafer-on-Substrate (CoWoS) are good packaging options. These devices and their printed circuit boards (PCBs) are designed to be thin and lighter for many applications and the severe warpage is one of the serious reliability concerns. The warpage has caused reliability issues such as soldering defects, bridging, stretching, head-in pillow, and non-wet opens. The warpage is caused by the CTE mismatches of the materials under temperature excursion during the manufacturing process of the package. Therefore, a good selection of materials or operating temperatures may help mitigate the deformation. Unfortunately, this type of warpage control is very difficult and complex for SiP, PoP, or McM packages because there are many components to be soldered together using different processing temperatures. To address the serious issue of warpage, we have developed a reflowable jig holder which can hold an array of MCM packages. Our jig holder is different from traditional ones that use end-clamping or only have clamp force in the inactive regions outside the functional package areas. Our reflowable jig holder implements magnets to apply forces on both inactive and active regions. With a Sm-Co magnet inside the reflowable jig at the bottom and a ferromagnetic cover on the top, we were able to better control the warpage. Experimentally, we have designed, fabricated, and tested four different magnetic jigs. Two different magnets having different diameters and weights, and two jigs with different thicknesses and materials were used. The magnetic flux densities and magnetic forces as a function of components’ structure or material were analyzed to optimize the performances. After the manufacturing of the packages with our innovative reflowable magnetic jig, the amount of warpage and shape of the package were inspected by Thermal Shadow Moire (TSM). The integrity of solder joints was inspected by X-ray and cross-section analyses. We have compared the warpage data of the packages using our innovative reflowable jig with those using a traditional reflowable jig. The experimental results show that the number of magnets and their configurations impact not only the local warpage but also the overall warpage. A reflowable jig with stronger magnetic force results in smaller warpage of the package. In conclusion, our innovative magnetic reflowable jig is a good method to control the warpage of these complex packages during the reflow process.