FLYER: fast fault simulation of linear analog circuits using polynomial waveform and perturbed state representation

Fault simulation is the critical approach for many applications such as fault detection & diagnostics, test set quality measurement, generation of test vectors, circuit testability, and many others along with the help of fault injection technique. The fault simulation approach is divided into many types. The most straightforward approach among them is a serial fault simulation. In the simulation process, the circuit under test is faulted, and a faulty copy is achieved by either using a simulator command technique or instrumentation technique. A fault simulator must examine the behaviour of specified target fault in design and classified as detected or undetected by the applied test patterns. To modify the original code is a very challenging and time-consuming task. Therefore, the RASP-FIT tool is developed, which alters the fault-free FPGA design, which is under investigation, at the Verilog HDL code level. It produces the copies of faulty design along with the top design file for several fault simulation methods. Using this tool, a serial fault simulation environment can easily be created with no much effort. In this work, a serial fault simulation method is verified and validated using the RASP-FIT tool for an ISCAS’85 benchmark design as an example.

The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SEESIM, based on the concept, demonstrated a performance superior to that of a state-of-the-art concurrent fault simulator, and comparable to that of parallel-pattern single-fault propagation simulators. It requires a minimal amount of memory and, because of its simplicity, can be easily extended to multilogic or higher level simulation.

Fault simulation is essential to design a high fault-coverage BIST. The simulation is characterized by combinational fault simulation and signature computation with a large amount of test patterns. In this paper, a fast fault simulator BISTSIM for BIST is developed. For the combinational fault simulation, a novel demand-driven logic simulation algorithm is proposed. Moreover, efficient fault propagation methods are incorporated into BISTSIM. The experimental results show that the proposed fault simulator delivers better performance than FSIM; about 2 to 3 times for circuits with a large number of test patterns. For signature evaluation of MISR to determine the aliasing, two efficient simulation methods, bit-array computation and parallel-pattern sequential simulation, are proposed. The resultant BISTSIM outperforms the fast fault simulator HOPE1.1 with an average speedup ratio of 10.

Test generation and fault simulation of path delay faults are very time-consuming. A new fault simulation method of fully enhanced scan designed circuits is proposed for path delay faults based on single stuck-at tests without circuit transformation. The proposed method identifies robustly and non-robustly testable paths first, for which a selected path circuit (SPC) is constructed. The SPC circuit contains no internal fanouts. Fault simulation of non-robustly testable paths is reduced to 3-valued logic simulation of the SPC circuit. Fault simulation is completed on the SPC circuit by only tracing the active part of SPC circuit. An effective fault dropping technique is also adopted based on the selective tracing scheme. The proposed fault simulation scheme is extended to that of robustly testable path delay faults. Experimental results confirm that the proposed fault simulator is exact. It is shown according to experimental results that the proposed fault simulator gets exact fault simulation results in very short time. Sufficient experimental results are presented to compare with previous methods on CPU time and accuracy.

The authors present a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The new algorithm attempts to reduce the computation time by processing many faults at a time on the assumption that a content addressable memory can be regarded as a single instruction multiple data (SIMD) type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is comparable to that of a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates. >

A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.

The authors describe fault simulation algorithms for the MARS hardware accelerator. Two algorithms are considered. The first, serial fault simulation, has a performance that is linear in the number of faults. Its performance is easily predictable and it takes full advantage of the true-value simulation speed of the accelerator; it is also easy to implement. The second algorithm, concurrent fault simulation, is found to have a performance that is nonlinear in the number of faults. It also requires either a large amount of memory or a dynamic memory management, both of which are difficult to implement in an accelerator. Yet the concurrent method has the advantage of more efficient event processing and less duplicated effort. Combining the features of both algorithms, a fixed-memory, multipass, concurrent algorithm is developed for MARS. >

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model physical failures found in an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing fast approximate switch-level fault simulation using transistor reverse level ordering, and a novel 9-valued switch-level extension to observability. The probability of propagation of a fault from an arbitrary line of the switch-level circuit to the primary output is shown to be a function of the average node fan-in and the line's distance to primary output. Using this probability, results show one order of magnitude of complexity speed-up as compared to traditional fault simulation techniques, while maintaining good accuracy.

The paper describes COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED results from coupling a parallel pattern simulator with a nonparallel simulator both working based on single fault propagation. Circuit partitioning and removing all feedback loops implemented into the parallel part of COMBINED result in a reduction of the number of events. In addition, the nonparallel part of COMBINED has been expanded either to detect more faults by introducing restricted symbolic fault simulation, or to reduce the number of events using PStar Algorithm which are also presented. COMBINED runs substantially faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.

Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information about the initial state of the circuit. In this case an unknown initial state is assumed which is usually handled by introducing a three-valued logic. As it is well-known fault simulation based on this logic only determines a lower bound of the fault coverage. Recently it has been shown that fault simulation based on the multiple observation time test strategy can improve the accuracy of the fault coverage. In this paper we describe how this strategy can be successfully implemented based on Ordered Binary Decision Diagrams. Our experiments demonstrate the efficiency of the fault simulation procedure developed.

A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit's behaviour is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with which we get rid of the time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that our serial fault emulator is about 20 times faster than HOPE. The speedup grows with the circuit size by our analysis. Two hybrid fault emulation approaches are also proposed. The first reduces the number of faults actually emulated by screening off faults not activated or with short propagation distances before emulation, and by collapsing nonstem faults into their equivalent stem faults. The second reduces the hardware requirement of the fault emulator by incorporating an ordinary fault simulator.

Fault simulation for sequential circuits numbers among the highly compute intensive tasks in the integrated circuit design process. In the quest for rapid design turn around, parallelization has been proposed to speed fault simulation. We introduce ProperPROOFS, a parallel extension of the PROOFS fault simulation package. ProperPROOFS exploits parallelism based on fault partitioning, incorporating static and dynamic partitioning schemes and a new asynchronous and distributed method of fault redistribution. We present results for circuits in the ISCAS-89 benchmark set across several parallel architectures. A detailed evaluation of results provides new insight into the use of fault partitioning to parallelize high performance serial fault simulation applications.

Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platform, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.

A new methodology called induced behavioral fault modeling is presented for fault simulation and testing of analog and mixed-signal circuits, and demonstrated using voltage controlled oscillators and phase-locked loops. The key of this methodology is to use actual layout and process defect information to derive a set of realistic faults at the transistor level, and to generate a small set of behavioral fault models-in a mixed-signal hardware description language-that abstracts the derived transistor-level faults. While ensuring the same fault coverage as transistor-level fault modeling, induced behavioral fault modeling offers significant advantage in simulation efficiency and modeling capacity.

To ensure resilient neural network processing on even unreliable hardware, comprehensive reliability analysis against various hardware faults is generally required before the neural network models are deployed, and efficient fault injection tools are highly demanded. However, many existing fault injection tools remain limited to basic fault injection and fail to provide fine-grained vulnerability analysis capability. In addition, many of the fault injection tools also need to change the neural network models and make the fault injection closely coupled with normal neural network processing, which complicates the use of these tools and slows down the fault simulation. The various fault injection implementations and error metrics make the comparison between different fault-tolerant studies difficult. To this end, we propose MRFI, a highly configurable multiresolution fault injection tool for deep neural networks. It enables users to modify an independent fault configuration file rather than neural network models for fault injection and vulnerability analysis. Particularly, it integrates extensive fault analysis functionalities from different perspectives and enables multiresolution investigation of the vulnerability of neural networks. In addition, it does not modify the major neural network computing framework of PyTorch. Hence, it allows parallel processing on GPUs naturally and exhibits fast fault simulation according to our experiments. Moreover, we also have the fault injection calibrated with fault simulation with architectural details and validate the accuracy of the proposed fault injection. Finally, MRFI is also open-sourced on GitHub (MRFI https://github.com/fffasttime/MRFI).