FPGA Auto Configuration Based on ATE

This research project aims to expand the capability of current US Navy Automated Test Equipment (ATE) family of testers known as the Consolidated Automated Support System (CASS). Industry research is now focused on breaking the historical construct of test equipment. Advances in the field of Synthetic Instruments have opened the door to test avionics in new ways. Every year new capabilities are developed using core hardware and increasingly capable software modules to create complex waveforms. This research creates a Digital Radio Frequency Memory (DRFM) Synthetic Instrument that can be programmed to perform a wide array of low latency Radio Frequency (RF) tests. Synthetic Instruments are defined as a concatenation of hardware and software modules used in combination to emulate a traditional piece of electronic instrumentation. This Synthetic Instrument couples high speed Analog-to-Digital Converters (ADC) to high speed Digital-to-Analog Converters (DAC) with Field Programmable Gate Arrays (FPGA) in between for digital signal processing. An RF front end is used to down convert the RF to baseband where it is sampled, modified, and up converted back to RF. The FPGA performs Digital Signal Processing (DSP) on the signal to achieve the desired output. Application of this DRFM in automated testing is demonstrated using a Reconfigurable Transportable Consolidated Automated Support System (RTCASS) tester at Naval Air Systems Command (NAVAIR) Jacksonville, FL. The Unit Under Test (UUT) is an ALQ-162 Defensive Electronic Countermeasures (DECM) receiver-transmitter. Ultra-low latency signals are generated to simulate enemy jamming stimulus. As the ALQ-162 detects and responds to the input, the DRFM switches to a new frequency. The time taken by the ALQ-162 to acquire, respond, and re-acquire is measured. This test confirms the internal Yttrium Iron Garnet (YIG) oscillator meets slew specifications. Currently Navy ATE can only test RF units using high latency steady state tests. This research project developed a supplemental unit that can be added to the VXI chassis in the CASS family of testers and conduct ultra-low latency active tests. The instrument acts as hardware-in-the-loop to perform real-time tests including a new capability to measure jamming response time from DECM avionics. Demonstrated performance capabilities include: latency <; 100 ns, output Spurious-Free Dynamic Range (SFDR) > 80 dBc, input SFDR > 60 dBc, frequency tuning resolution <; 2 Hz, and frequency settling time <; 0.5 ns. New RF capabilities developed by this effort parallel similar research ongoing for digital test instruments like the Teradyne High Speed Subsystem. Incorporating this Digital RF Memory synthetic instrument into current and future ATE will improve readiness and supportability of the fleet. Improvements demonstrated by this research project will expand the type and quantity of assets able to be tested by current and future ATE.

System testing is one of the test stages of a software test, making sure that the software intended for the system is working as it should be. This study has aimed to automate the manual system testing of the Field Programmable Gate Array (FPGA) -based ADC reference design boards together with its corresponding software. Test scripts were developed for the automation of two ADC boards which was tested to five different versions of Linux image and boot files. Both were executed on the manual system test setup and automated system test set up and the test time and parameter result were recorded. The study was able to show that the test execution time of the automated system test is significantly faster compared to the manual system test without compromising the accuracy of the measured parameters.

A solution for testing fast-switching bidirectional signal lines using an array of technology-specific transceivers has been described previously (1998). This method uses an active component located between the device-under-test (DUT) and the automated test equipment (ATE) to reduce electrical interconnect delays to less than 150 ps. In this paper, the transceiver array concept is extended to include higher-level test processes such as real-time algorithmic pattern generation (APG), multi-gigahertz signal multiplexing, and others. The active test component is therefore called a "Test Support Processor" (TSP). It greatly reduces the functionality and performance capability required of the ATE, while maintaining signal integrity, and improving overall test quality. In its minimum configuration, the TSP provides an array of technology-specific transceivers very close to the DUT. This reduces transmission line effects, allowing for at-speed test of fast I/O switching characteristics. This technique may lead to lower-cost. The TSP is specifically intended to complement and support existing DFT and BIST structures within the DUT. The use of the TSP provides an additional degree of freedom for partitioning the test problem, and may result in a significant paradigm shift for future ATE architectures. This paper describes variations of the TSP concept, its potential applications, and economic impact. Three variations are illustrated through prototype demonstrations, including: (A) a 2.67 Gbps test pattern source, (B) a transceiver array for testing a high speed 4 Mbit SRAM, and (C) a reconfigurable real-time APG for memory testing, implemented using a field-programmable gate array (FPGA).

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The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.

Compared with the four-phase optical structure, the grating encoder based on two-phase optical structure reduces the number of optical devices used in the system and makes the system more compact. Due to the high requirements for realtime and parallel processing of algorithm solution, the powerful parallel computing ability of Field Programmable Gate Array (FPGA) and customized hardware acceleration algorithm are needed to improve the real-time performance. In the previous research, the displacement signal generated by the grating encoder can be input into the FPGA through analog to digital converter (ADC) sampling, and then complete self-designed filter filtering, phase correction and displacement solution. In this paper, further, the ADC sampling rate adjustable interface is added to the FPGA, the global signal and the dc offset remove algorithm is added, and the displacement solution results in the form of fixed-point number are output to the host computer through the MicroBlaze (MB) soft core. MB core can realize process control and interface conversion on FPGA, and use a small amount of logic resources to replace the functions of MCU and DSP of traditional embedded measurement system, so as to further improve the integration of the instrument. A series of experiments are carried out on the two-phase FPGA platform. ADC sampling rate is 200ksps, 8-Channel synchronous parallel sampling, FPGA system clock frequency is 200MHz. The linear displacement table is set to drive the measurement grating at different displacement speeds, and the total stroke is set to 10mm. The FPGA real-time displacement solution platform is tested. The experimental results show that FPGA obtains accurate displacement solution results under different speed tests. In the test of 2 mm/s, the maximum cumulative displacement measurement error is 5um, which shows the real-time performance and accurate displacement solution performance of FPGA platform.

The Arbitrary Waveform Generator (AWG) is an important instrument that is widely used in automatic test equipment, radar system, and other fields for generating complex signals. The increasing demand for waveform's complexity is consisted of repeatable segments and advanced-segments, where each segment or segments group could be repeated multiple times. Those requirements make the existing design, implemented by an address generator, complex. The software defined technology can separate the instruction sequence processing from the Data plane to the Controller where the complex logic is defined by software, which lead to a simplified data plane. This paper proposes a design that will generate complex arbitrary waveform by decoupling the waveform composing logic in address generator out from the data plane as an instruction controller. The controller support instruction sequence defined by segment and a jump instruction, which can implement the repeatable segments and the advanced-segments, respectively. We built an AWG based on this design and made the implementation in a field programmable gate array with a required clock frequency of 125 MHz. The design has a high sampling rate of 4 gigabit samples per second and can generate complex arbitrary waveform consisting of repeatable segments and advanced-segments.

Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especially for low-cost device. One of the major factors of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithms have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this example, approximate 33% of test time reduction observed for 1 Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow.

Introducing new communication equipment or system to the Tracking and Data Relay Satellite System (TDRSS) ground segment is a complicated process that involves a lengthy development and test cycle. Complexity arises due to the presence of the variety of signaling formats, operation and user constraints, monitor and control parameters, and the requirement to ensure the new piece of ground equipment or system meets the functional and performance requirements for all different combinations of system configuration parameters and operational scenarios. The development cycle starts with extensive software simulations to establish the performance parameters of the new equipment or system followed by a prototyping stage. The prototype system undergoes a battery of tests in a laboratory environment to verify that it is capable of meeting the performance levels derived from the software simulations. Testing must be performed using simulated signals generated either using software or hardware. The current practice is to use a chain of test equipment, each piece in the chain dedicated to a single function. This requires manual setup between different test configurations and test reporting is also handled manually. This is costly both in terms of test hardware investment and the manpower involved. The options available to reduce the cost are to use either a software or hardware simulator that can combine multiple functions in a single unit. Software simulation involves generating signal files that can be played back repeatedly. Depending on the data rate being simulated, each test file can occupy several Terabytes (TBs); in addition, it requires a playback system which tends to be relatively expensive to acquire and maintain. On the other hand, with more advanced signal processing technology the hardware simulation can be achieved with low cost Field Programmable Gate Array (FPGA). A low cost hardware simulator that can support data rates up to 25 Mbps is selected for the simulation system. The simulator supports baseband digital data formats and different modulation and coding schemes used in the TDRSS. Channel impairments applicable for communicating with orbiting platforms and signal impairments generated by the TDRSS itself are also simulated by the system; these include stressing profiles of delay, Doppler, and multipath. Hardware distortions of customer platforms are simulated by a set of software defined distortion filters designed according to the user constraints specified in the Space Network user's guide. In order to reduce the time spent during the prototype testing phase, an automated test system is being developed. Simulator architecture and the test automation approach will be presented.

Faced with ever-increasing constraints of budget reductions and fight schedules, test engineers are looking for faster, more cost-efficient ways to get automatic test equipment (ATE) systems up and running. This case study examines a process known as Freedom/sup TM/ Series, developed by Racal Instruments, illustrating how the principles of design reuse and automation, applied to ATE systems, can dramatically reduce non-recurring engineering costs and accelerate schedules. Freedom Series is a modular approach to ATE system design. It exploits design reuse by standardizing components such as test instruments, interface cables, software drivers, and documentation. In addition, Freedom Series provides software tools that automate many non-recurring engineering tasks. The combination of modularity, reuse, and automation accelerates the system integration process and, in many cases, virtually eliminates non-recurring engineering costs.

Traditionally, automated test equipment (ATE) manufacturers have been producing test systems to meet the needs of the electronic industry and research organizations. There is however another fairly large ATE market that has not been addressed by ATE-educational institutes and universities. Issues related to the electronic test equipment for educational institutions are discussed in this paper. It identifies the requirements to implement a test engineering program in the university environment, the challenges that face both university and industry, and strategies that can be adopted to meet these requirements. It provides a general roadmap that allows customization to suit emerging test engineering developments that may occur future. Consideration is given to a pragmatic, and cost effective collaboration between the academic and industrial worlds.

Virtual test (VT), allowing the verification of test programs and associated test hardware in a simulation environment before silicon and without a real automatic test equipment (ATE), has proven to be an effective technique to cut time-to-market and costs for mixed-signal system on chip (SoC), even in an industrial environment. Mixed-signal VT requires behavioral models both for the device under test (DUT) and the device interface board (DIB), interfacing the DUT with the ATE. Test engineers are used to design the DIB circuitry in detail. The resulting schematic is used for the layout and manufacturing of the DIB. In order to develop a behavioral model of the DIB, the test engineer has (1) to abstract this low-level schematic, by identifying the relevant functions and signal flows, and (2) to write the model manually. This bottom-up procedure is very time consuming and may lead to inconsistencies and errors. This paper introduces a new top-down flow for DIB development, allowing the automatic generation of the DIB behavioral model using VHDL as the modeling language. Test engineers enter the design of the DIB by a schematic entry tool at a very abstract level (i.e. as a block diagram). Using specific libraries, test engineers can then generate the real circuit schematic or VHDL model by dedicated netlisters.

Field Programmable Gate Arrays (FPGAs) are designed and fabricated using the most advanced CMOS technology nodes to meet performance and power demands. This makes them susceptible to many manufacturing and reliability challenges. Increasing chip temperature is a major reliability concern since various failure mechanisms are accelerated at high chip temperature, which require thermal-aware testing to detect them. External devices like thermal chambers are usually used to heat up the chip to a desired temperature in order to apply the test. However, there are many limitations for these external devices, which make the thermal-aware testing of the FPGA a challenging process. In this paper, a self-heating approach for thermal-aware testing of FPGAs is presented, in which the internal resources of FPGA are used to build controlled self-heating elements (SHEs). These controlled SHEs are distributed across the FPGA and integrated with the built-in self-test (BIST) scheme to generate the required temperature profile for testing. Thus, no external devices for heating up the FPGA are needed. The experimental results show that a wide range of maximum chip temperatures can be achieved (from 50°C up to 125°C on Virtex-5 FPGA) with a high accuracy (±1°C).

Conventional seismic processing is performed on a CPU with 32 or 64-bit precision for all operations. In certain cases, using a reduced precision produces equivalent result within acceptable tolerances. However, as CPUs do not support configurable bit-widths, reducing precision brings no benefits to performance. In contrast, Field Programmable Gate Arrays (FPGA) enable application specific number representations. With hardware support for reconfigurable number format and bit-width, reduced precision can greatly decrease the area cost and I/O bandwidth of the design, thus multiplying the performance with concurrent processing cores on an FPGA. In this paper, we present a tool to determine the most appropriate number format for a given seismic application. We demonstrate the methodology on a source-receiver downward continuous based migration. The acceleration device is a Maxeler Technologies MAX-1 card containing a Xilinx Virtex-4 FPGA and connects to a PC over a PCI Express bus. Using optimized number representations, we can implement two concurrent processing cores on the FPGA, and achieve a speedup of 14 times compared to a Intel Xeon 1.86GHz CPU. Moreover, with sufficient bandwidth between the CPU and FPGA, we show that a further increase to 48x speedup is possible.

In this paper an implementation of the Inverse Numerical Laplace Transform (INLT) on a Field Programmable Gate Array (FPGA) is presented. A brief description of INLT algorithms based on FFT are made and its MATLAB implementation is performed in order to have a comparison basis with FPGA results. A fixed point representation is used and it is optimized using fi MATLAB object. INLT is basically composed by three stages: Windowing, FFT and exponential function multiplications, the last stage is considered the critical one because it can result in severely large errors, specially, when several samples are required. Errors can be reduced by increasing the number of bits, however this increment makes the required FPGA area greater. Windowing and FFT can be implemented with high accuracy on FPGA with CORDIC and Cooley Tukey algorithms respectively, making the implementation flexible. The implementation was made with Verilog description hardware language using Xilinx technology and Virtex 6 FPGA.