FPGA Implementation for Hyperspectral Target Detection with Adaptive Coherence Estimator

A common problem in applying lossy compression to a hyperspectral image is predicting its effect on spectral target detection performance. Recent work has shown that light amounts of lossy compression can remove noise in hyperspectral imagery that would otherwise bias a covariance-based spectral target detection algorithm’s background-normalized response to target samples. However, the detection performance of such an algorithm is a function of both the specific target of interest as well as the background, among other factors, and therefore sometimes lossy compression operating at a particular compression ratio (CR) will not negatively affect the detection of one target, while it will negatively affect the detection of another. To account for the variability in this behavior, we have developed a target-centric metric that guides the selection of a lossy compression algorithm’s CR without knowledge of whether or not the targets of interest are present in an image. Further, we show that this metric is correlated with the adaptive coherence estimator’s (ACE’s) signal to clutter ratio when targets are present in an image.

Hyperspectral image contains various wavelength channels and the corresponding imagery processing requires a computation platform with high performance. Target and anomaly detection on hyperspectral image has been concerned because of its practicality in many real-time detection fields while wider applicability is limited by the computing condition and low processing speed. The field programmable gate arrays (FPGAs) offer the possibility of on-board hyperspectral data processing with high speed, low-power consumption, reconfigurability and radiation tolerance. In this paper, we develop a novel FPGA-based technique for efficient real-time target detection algorithm in hyperspectral images. The collaborative representation is an efficient target detection (CRD) algorithm in hyperspectral imagery, which is directly based on the concept that the target pixels can be approximately represented by its spectral signatures, while the other cannot. To achieve high processing speed on FPGAs platform, the CRD algorithm reduces the dimensionality of hyperspectral image first. The Sherman–Morrison formula is utilized to calculate the matrix inversion to reduce the complexity of overall CRD algorithm. The achieved results demonstrate that the proposed system may obtains shorter processing time of the CRD algorithm than that on 3.40 GHz CPU.

Target detection is a key issue in processing hyperspectral images (HSIs). Spectral-identification-based algorithms are sensitive to spectral variability and noise in acquisition. In most cases, both the target spatial distributions and the spectral signatures are unknown, so each pixel is separately tested and appears as a target when it significantly differs from the background. In this paper, we propose two algorithms to improve the signal-to-noise ratio (SNR) of hyperspectral data, leading to detectors that are robust to noise. These algorithms consist in integrating adaptive spatial/spectral filtering into the adaptive matched filter and adaptive coherence estimator. Considering the HSIs as tensor data, our approach introduces a data representation involving multidimensional processing. It combines the advantages of spatial and spectral information using an alternating least square algorithm. To estimate the signal subspace dimension in each spatial mode, we extend the Akaike information criterion, and we develop an iterative algorithm for spectral-mode rank estimation. We demonstrate the interest of integrating the quadtree decomposition to perform an adaptive 3-D filtering and thereby preserve the local image characteristics. This leads to a significant improvement in terms of denoised tensor SNR and, consequently, in terms of detection probability. The performance of our method is exemplified using simulated and real-world HYperspectral Digital Imagery Collection Experiment images.

Target detection (TD) is a major task in hyperspectral image (HSI) processing which, due to the high spectral resolution, requires dealing with the curse of dimensionality. The integrated feature extraction and selection is a well-known solution for dimensionality reduction of HSIs. In this study, a new method is presented to improve the performance of TD algorithms based on principal component analysis (PCA) feature space. In this method, using the implantation of the target spectrum (TS) in the HSI and following the simulated targets in the PCA feature space, the best principal components (PCs) are selected. Then, using the mixing and unmixing coefficients of the PCs, a new TS and a new image in the PCA feature space are created. Afterwards, using the new spectrum of the target, the TD algorithm is run on the new HSI. The performance of the proposed method is compared to nine counterpart algorithms on Hymap and Hyperion HSI. All the comparisons are performed using adaptive coherence estimator (ACE) TD algorithm. Experimental results illustrate that the proposed method, compared to its counterparts, yields superior performance based on the false alarm rate (FAR) measure. It gives an average FAR value of about 16, which is approximately 9% better than that of its best counterparts.

This study introduces case adaptive detection models for detecting asbestos-containing building materials employing short-wave infrared hyperspectral images. The models are optimized for indoor and outdoor conditions, which could be applied to asbestos detection in interior and exterior building materials. Samples were collected from the most probable types and forms of building materials for both asbestos-containing materials (ACMs) and non-asbestos-containing materials (non-ACMs) to represent real-world conditions, utilizing the largest and most diverse dataset to date (11 types, 4 directions, and 4 forms). X-ray diffraction (XRD), scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) analyses demonstrated that chrysotile was the main asbestos mineral in the most of ACMs, as evidenced by characteristic chrysotile diffraction peaks, fibrous serpentine morphology, and coincident Mg-Si elemental distributions. The spectral characteristics of building materials are manifested by mineral components for ACMs and non-ACMs, where asbestos absorption (Mg-OH) identifies ACMs. The indoor RF model identified critical absorption features at 2299-2350nm, 1923-1967nm, and 2366-2426nm, corresponding to Mg-OH, OH, and CO₃²⁻ absorptions, achieving 95.3% accuracy. The outdoor RF model incorporated additional Fe-OH and Al-OH bands, achieving 96.5% accuracy. Real-world validation at three asbestos abatement sites and one large-scale site demonstrated practical applicability including scalability and computational efficiency with overall accuracies of 92.1% for indoor and 92.5% for outdoor conditions. Comparative analysis with existing benchmark methodologies confirmed superior performance, with our models significantly outperforming previous approaches. The models successfully detected ACMs across various material conditions, scales and effectively verified complete removal post-abatement with high computational speed. This approach delivers immediate practical value for compliance verification and quality assurance in real-world abatement scenarios and large-scale surveys, providing objective documentation for regulatory compliance while substantially reducing costs compared to conventional destructive sampling methods.

Because of its high computation speed, shorter Because of its high computation speed, shorter design period, and higher density, the use of Field Programmable Gate Array (FPGA) has gained a lot of attention in the design and practical implementation of PWM (Pulse width modulation) techniques for MLI (Multilevel Inverter) structures. PWM techniques are designed to reduce switching losses, voltage stress of switches, total harmonic distortion (THD) and to increase the number of output voltage levels of inverter structures. This paper presents an Automatic Pulse Sequence Selector (APSS) for the Novel PWM technique by using FPGA LabVIEW software. The pulse sequence selection is done by using the sample index generated by the reference sinusoidal wave. By the automatic selection of specific pulse sequences from the sequences, the output wave of the inverter structure will be closer to the reference sinusoidal wave. The THD of the inverter output wave will be less than compared to direct feeding of those pulses to MLI structures. Using MATLAB/Simulink, a simulation study is performed on developed MLI structures for the validation of the proposed design. Comparison between the FFT analysis of these inverter structures verifies the efficacy of the design.

Hyperspectral imaging (HSI) can extract information from scenes on the earth surface acquired by airborne or spaceborne sensors. On-board processing of HSI is characterized by large datasets on one side and limited processing time and communication links on the other. The CCSDS-123 algorithm is a compression standard assembled for space-related application that allows compacted data transmission via a transmission link. In this paper, a low-complexity high-throughput field-programmable gate array (FPGA) implementation of CCSDS-123 compression algorithm with band interleaved by pixel ordering is presented. Hardware accelerators implemented in FPGAs are increasingly used for custom tasks due to their efficiency, low power, and reconfigurability. The proposed implementation of CCSDS-123 compression standard has been tested on ZedBoard development board containing a Zynq-7020 FPGA. The results are verified against an existing software implementation. The synthesized design can perform on-the-fly processing of hyperspectral images with maximum operating frequency of 147 MHz. The achieved throughput of 147 Msamples/s (2.35 Gb/s) is higher when compared with the throughput reported in recent state-of-the-art FPGA implementations.

Independent component analysis (ICA) is a technique that extracts independent source signals by searching for a linear or nonlinear transformation which minimizes the statistical dependence between components. ICA has been used in a variety of signal processing applications including dimensionality reduction in hyperspectral image (HSI) analysis. Due to the computation complexities and convergence rates, ICA is very time-consuming for high volume or dimension data set like hyperspectral images. Hardware implementation provides not only an optimal parallelism environment, but also a potential faster and real-time solution. This work synthesizes a parallel ICA (pICA) algorithm on field programmable gate array (FPGA). In the proposed implementation method, the pICA is partitioned into three temporally independent functional modules, and each of which is synthesized individually with several ICA-related reconfigurable components (RCs) that are developed for reuse and retargeting purpose. All modules are then integrated into a design and development environment for performing many subtasks such as FPGA synthesis, optimization, placement and routing. In a case study, we synthesize the pICA algorithm for hyperspectral image dimensionality reduction on the pilchard reconfigurahle computing platform embedded with Xilinx: VIRTEX V1000E. The FPGA executes at the maximum frequency of 20.161 MHz, and the pilchard board transfers data directly with CPU on the 64-bit memory bus at the maximum frequency of 133MHz. The performance comparisons between the proposed and another two ICA-related FPGA implementations show that the proposed FPGA implementation of pICA has potential in performing complicated algorithms on large volume data sets.

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application. The conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGA have higher speed and smaller size for real time application than the VLSI design. The challenges are finding an architecture that minimizes the hardware cost, maximizing the performance, accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design was tested on a FPGA demo board. Keywords- Backpropagation, field programmable gate array (FPGA) hardware implementation, multilayer perceptron, pressure sensor, Xilinx FPGA.

On-board reconfiguration of FPGAs on a spacecraft offers the important advantage of allowing the reuse of the same hardware component for different functionalities during a mission. To be able to benefit from these features, a solution to cope with the challenges of using SRAMbased FPGAs in a radiation environment is required, and at the same time it is desired that the FPGA reconfiguration takes place at high speed. The BRAVE NG-MEDIUM FPGA offers a solution for this problem, by combining being radiation-hardened by design and reconfiguration of the programmable logic via a high-speed communication protocol, namely SpaceWire. In this paper we compare the performance of SpaceWire with Joint Test Action Group (JTAG) for NG-MEDIUM reconfiguration, in terms of the time elapsed when uploading a bitstream file from a Central Processing Unit (in our case from a computer) to the Field Programmable Gate Array (FPGA) and the time needed for uploading such bitstream and configuring the FPGA with the uploaded bitstream.

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely.

Fuzzy controllers are known as one of the most useful controllers in the industry. Fuzzy controllers have significant characteristics such as simple structure and being imprecision in input variables. The mentioned features would be more indispensable in the nonlinear system, especially in DC motors. Field Programmable Gate Arrays (FPGAs) are one of the equipment for implementing fuzzy controllers. FPGAs have brilliant privileges such as high speed in mathematical computation and doing tasks simultaneously. Although doing tasks as pipeline provide an excellent opportunity for increasing the speed of circuits, it creates a hard situation for implementing a control unit to control the other blocks (such as blocks used in the fuzzy controller of DC motors, which encompass several computational blocks). This paper firstly focuses on the structure of a fuzzy controller for DC motors, which are implemented on FPGA optimally. Secondly, an optimized controller, based on a personalized microcontroller, introduced for managing the data flow and the outputs of computational blocks of a fuzzy controller that is implemented in FPGA. The proposed microcontroller significantly reduces the complexity and time needed for implementing a fuzzy controller on FPGA.

The use of an automated Data Acquisition System (DAS) is very important in testing and measurement systems. The desire is extremely high in the DAS with high speed, multi-channel, and large capacity, so research in this area becomes very significant. The growing problem in DAS is to acquire the data with the required data rate and store data onto the on-chip memory. Microcontroller, microprocessor or Digital Signal Processors (DSP) devices can be programmed as a DAS, but these devices comprise problems, such as slower data acquisition rates, nonavailability of sufficient on-chip memory, etc. To overcome these above drawbacks, this paper provides an approach to design and develop DAS based on the Field Programmable Gate Array (FPGA). To acquire the data from Analog to Digital Converter (ADC) to FPGA, an Inter Integrated Circuit (I2C) serial communication protocol is used. I2C master communication protocol is designed and developed using VHDL with the Quartus II version 13.1, and the I2C master protocol is implemented in cyclone III FPGA. FPGA is acting as a master controller. DAS with the FPGA will provide the better acquisition results compared to the existing acquisition system.

The high processing speed and reconfigurable features of FPGA (Field-Programmable Gate Array) make it the first choice for acceleration chip. Currently, the CPU/FPGA hybrid architecture is a research hotspot in improving hardware processing speed. Many companies have investigated in related researches. However, the current researches have not solved the coordination problem between CPU and FPGA in this architecture. The Communication efficiency problem between CPU and FPGA is the key to the failure of hardware performance. Some of the current researches are mainly to optimize the communication protocol between CPU and FPGA to improve data transfer rate. This paper proposes a different method to reduce the frequency of communication between CPU and FPGA for this problem. The processing speed of the architecture is improved by simplify communication between the CPU and the FPGA. This approach reduces communication frequency between the CPU and the FPGA by splitting the software into hardware master thread and slave threads that can run independently run on the FPGA. The CPU only needs to configure the FPGA at the beginning and retrieve the result from the FPGA at the end. No communication is required during FPGA running, thereby reducing unnecessary communication waste.

Memory which is used for searching applications, like Network routers, operating at a higher speed is called Ternary Content Addressable Memory (TCAM). The requirement of TCAM is gradually growing in the searching field applications. TCAM memories are usually built in ASIC (Application Specific Integrated Circuit) which offers searching operation at a higher speed in a predetermined time but is expensive in cost. TCAMs designed on FPGAs (Field Programmable Gate Array) experience high power consumption, larger use of FPGA resources, and suffer from the inefficiency of storage. TCAM using multipumping and multiported SRAM is designed for achieving an effectual use of FPGA resources, and a reduction in usage of power and area. In the present SRAM based TCAM designs, there is an exponential growth in memory usage due to the increase in the patterns of TCAM, which is reduced by cascading the multiple blocks of SRAM (BRAMs) in FPGA that makes growth linear. BRAMs of FPGAs have restrictions in depth, which restricts the effectual storage of TCAM bits. In this paper, a modified TCAM design is proposed which avoids this restriction by using shallow sub-blocking of BRAMs. The design proposed in this paper operates the multiported SRAM by using the dual-port BRAM and by clocking it internally at a higher frequency using multipumping technique which allows access of the BRAM subblocks in one cycle of the system clock. These modifications in the divisional traditional TCAM table results in an effectual design of TCAM memory. The proposed design is coded in Verilog and simulated using the Xilinx ISE tool and was implemented on a Virtex 7xc7vx485 FPGA device. The proposed design has better performance, in terms of 26% reduction in power and 7% reduction in area, as compared to existing SRAM based TCAM design.