FPGA Implementation of High-Efficiency ECC Point Multiplication Circuit

Embedded systems carry and process more and more sensitive information in untrusted environments, where an attacker can wiretap the external communication and also has unlimited physical access to the device. Cryptography protects systems against many of the threats and relies on the security of the cryptographic keys inside the system. Physical Unclonable Functions (PUFs) measure manufacturing variations inside integrated circuits, for example FPGAs, to generate a unique secret PUF response inside each device. Similar to deriving a biometric pattern from human features, the individual pattern inside an FPGA differs slightly from measurement to measurement. From these measurements, the PUF response is generated to derive a secure and reliable cryptographic key. The Ring-Oscillator (RO) PUF is a popular PUF type because of its high randomness and reliability. Frequencies of ROs are compared pairwise to derive one secret bit. So far, the reliability of RO PUFs was evaluated by counting bit flips in measured PUF responses. This work analyzes the distribution of frequency measurements to derive the behavior of the PUF. Analyzing the frequency distributions gives a more precise estimation of the PUF bit error rates than measuring the bit errors after the comparison of two oscillator frequencies. The evaluation of publicly available real world empirical FPGA data has shown that most error probabilities of RO PUF responses are so low that they cannot be measured in feasible time. For almost 200 evaluated FPGAs, more than 70% of the PUF outputs on every FPGA have bit error probabilities under 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-20</sup> . We can even ensure this error probability for over 60% of the PUF outputs after a practicable number of frequency measurements with a confidence of 99.9%. Index Terms-Physical Unclonable Functions (PUFs), Ring Oscillator PUF, FPGA, Statistics.

In this work, we examine the spatial auto-correlation exhibited in the responses of memory-based Physical Unclonable Functions (PUFs). In particular, we examine the responses of an SRAM PUF, a DRAM decay-based PUF, and a disturbance-based Flash PUF. For the evaluation, we use three different metrics that have already been employed in the relevant literature for measuring the spatial correlation of other PUF responses. Our results prove that the examined PUF responses exhibit little, if any, spatial auto-correlation. Thus, these PUFs can be considered as security mechanisms of high entropy, which can be utilised to enhance the security of the Internet of Things (IoT).

Internet of Things (IoT) as a ubiquitous paradigm is a new concept in Information and Communications Technology (ICT) and has the ability to connect wireless and mobile embedded devices and things to the Internet. IoT is emerging as a key component of the Internet and a vital infrastructure for millions of smart and interconnected objects that are potentially vulnerable to different attacks. Thus, the security of resource-constrained devices in IoT is highly important. As an important solution, cryptographic algorithms are used to provide confidentiality and integrity of the transmitted data between the sender and receiver. Hence, this paper proposes a new hybrid cryptographic algorithm based on Rivest cipher (RC4), Elliptic-Curve Cryptography (ECC), and Secure Hash Algorithm (SHA-256) to protect sensitive information in IoT-based smart irrigation systems. In this paper, the RC4 key is encrypted by the ECC algorithm, and the output of this encryption process is transformed to SHA-256 for hashing and generating enigmatic data. SHA-256 algorithm encrypts RC4 based cipher text to improve data integrity. Comprehensive analysis and simulation results indicate that the proposed scheme is secure to various known attacks such as the Man-in-the-middle (MiM) attack, and has a better performance than other cryptographic algorithms. Also, the obtained results confirm the effectiveness of the proposed model and robustness in order to confidentiality based on analyzing secrecy.

In this paper, we propose a novel parallel Elliptic-Curve-Cryptography (ECC) point multiplication implementation over binary Galois Field, GF(2m) by exploiting the advantage of concurrent operation in a homogeneous multi-core processor to yield an improved performance. A modified Lopez-Dahab (LD) mix-coordinates point multiplication algorithm is developed that exploits concurrency and enables operation using parallel instructions. The algorithm is used to implement ECC point multiplication over GF(2^163) on an Xmos multi-core microcontroller. The results obtained show a 60% performance improvement can be achieved over a single core implementation. Our presented implementation is believed to be the first parallel implementation of ECC scalar point multiplication over binary fields on a homogeneous multi-core microcontroller.

Mobile ad hoc network (MANET) is a group of mobile nodes that communicates with each other without any supporting infrastructure. These networks have some unique features such as dynamic mobility, open nature, lack of infrastructure, limited physical security and they are vulnerable to several security threats. Malicious node can drop all or partial received packets instead of forwarding them to the next hop through the path. In order to find the malicious nodes, an initial transmission is made between the source and destination nodes. Using fuzzy rules, the trust value of each node is computed and it varies from 0 to 1. A common threshold value is set for each node and by using this threshold value, every node in the network can be identified as either a malicious node or a regular node. After identifying the malicious nodes, these nodes are eliminated by muting the power to off state. As the malicious nodes are eliminated between source and destination nodes, source node can select another trusted path to its destination&#x0D; node. For security and authentication of routing information, hybrid cryptography is employed, using advanced encryption standard (AES) and elliptic curve cryptography (ECC) algorithms. AES algorithm is used as symmetric algorithm to encrypt the routing information and ECC algorithm is used as asymmetric algorithm to encrypt the public key. During encryption, the original plain text is converted into cipher text with encrypted public key and similarly during decryption cipher text is converted into original plain text with decrypted private keys. So the proposed method involves both AES and ECC algorithms which provides security mechanism as efficient and sufficient one. The experimental simulations are carried for the proposed model using network simulator 2 (NS-2) for Throughput, Delay, Packet delivery ratio, Packet overhead and Packet drop.

The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach.

A new concept for Physical Unclonable Functions (PUFs), the Mirror PUF, is proposed. The Mirror PUF can be applied to existing preselected PUF circuits by post-processing the preselection test results and has the potential to double the number of effective bits, with no additional area at the bit-cell level. The Mirror PUF utilizes a preselection test, which measures the amount of mismatch within the PUF cell. This data is generally used to determine the mask for a conventional PUF. Here, it is used as an entropy source that is not correlated to the original response of the PUF. Bit-cells with low mismatch are considered as a ‘0’ and cells with high mismatch as a ‘1’. A systematic method is shown for identifying unstable bits in the Mirror PUF response. It classifies the cells to ‘low’, ‘medium’ and ‘high’ mismatch, such that medium mismatch bits are considered as unstable and masked from the response. The concept was applied to a 65nm Si implementation of the Capacitive Tilt PUF (Shifman et al., 2020). All of the unstable cells of the Mirror PUF, except for 0.03%, were identified and masked, with a worst-case corner Bit Error-Rate (BER) of only 2.35E-5 and 0.00026% erroneous responses across all corners. The application of the Mirror PUF to the Capacitive tilt PUF increased the number of stable response bits by 66%. No observable correlation was found between the responses of the original PUF and the Mirror PUF.

The use of physically unclonable functions (PUFs) as a new cryptographic technique is gaining attention. Challenge-response authentication and key generation (key storage) are well known as major applications using PUFs. When PUFs are applied to these applications, min-entropy estimation is essential. The min-entropy is a measure of the lower bound of the unpredictability of PUF responses. Many studies have estimated the min-entropy of PUFs, and several of these studies dealt with PUFs with independent and identically distributed (IID) PUF responses. Few studies have focused on non-IID PUFs. One reason is that some causes of entropy loss are complicatedly intertwined, and the entropy estimation of non-IID PUFs is hard. Thus, it is first necessary to break down the intertwined causes to estimate min-entropy. In this paper, we present typical causes of entropy loss during PUF implementation and propose a cause analysis method using the Inter-Hamming distance (HD), which is one of major performance metrics of PUFs. And the proposed method was applied to prototyped PUFs designed with a 180-nm CMOS process. We demonstrate that the causes of entropy loss on each PUF can be broken down according to the analysis results.

A Physical Unclonable Function (PUF) is a die specific random function that can be used in a number of secure IC applications including die identification/authentication and key generation. At the core of a silicon PUF is a circuit (the PUF core) that generates random bits. These bits are like a silicon biometric, unique across dies, but can be reliably reproduced multiple times on a die across voltage and temperature variations and aging. In this thesis, we discuss various aspects of a PUF design, with a strong focus on circuit details. We describe the properties and the figures of merit of a PUF and then compare various PUF core implementations. We identify the biggest design challenges and provide several solutions. Results in this work are supported by measurement data from testchips designed in 65nm bulk CMOS. We provide an apples-to-apples comparison of various PUF implementations. We demonstrate that while adequate randomness and uniqueness is achievable for most PUF implementations, achieving high reliability is a challenge. The conventional method to achieve high reliability is to use error correcting codes (ECC). Unfortunately, the overheads associated with these techniques grows very quickly with error correction capability. Alternately, researchers have proposed several error reduction techniques to minimize the use of error correction. In this work, we evaluate four orthogonal and complementary error reduction techniques. Two of these techniques, categorized as extrinsic techniques, are multiple evaluation (ME) and activation control (AC) and are able to reduce errors in PUF response by ~70-80%. The other two techniques, categorized as intrinsic, are post-silicon selection (PSS) and directed accelerated aging (DAA) and show ~100% correction of errors. As a proof of concept prototype, we describe a self-contained, BIST-controlled key-generator that implements the PSS technique to autonomously generate bits with a bit error rate &lt; 5 * 10^-9, equivalent to a 128-bit key error rate &lt; 10^-6. We also describe a realization of a strong-PUF that uses these highly reliable bits in conjunction with an Advanced Encryption Standard (AES) primitive.

This manuscript addresses a novel MRAM-based physically unclonable function (PUF). The PUF responses are generated using the unique energy-tilt, which is an outcome of the random geometric variations in the MRAM cells. We have verified relevant attributes of this PUF through extensive magnetic simulations and in-house fabrication results. Our fabricated PUF cells generate entropy as high as 0.99, which is comparable to most of its competitors. To our knowledge, the footprint of the PUF cells is also lower than the majority of silicon PUFs. Also, the authentication control algorithm for this PUF requires very low additional control-steps. We conclude our discussion of this novel PUF with a study of authentication overhead and protocols required by the PUF system in terms of area, power, and delay.

The silicon primitives known as Physically Unclonable Functions (PUFs) are used for various security purposes including key generation, device authentication, etc. Due to the imperfections in manufacturing process, PUFs produce their unique outputs (responses) for given input signals (challenges) fed to identical circuitry designs. Although PUFs are deployed to preserve security and are assumed to be unclonable, their functionality may still be compromised by modeling attacks. However, such attacks only target one single PUF aiming at reversing its behavior (based on a subset of its challenge-response pairs), and are not useful for attacking other PUFs. Moreover a subset of the target PUF's response has to be known by the attacker. This paper moves one step forward and investigates the possibility of Cross-PUF attacks in which a particular PUF's power fingerprints can be used to break another PUF's security. In these Cross-PUF attacks, the attacker has at his disposal a reference PUF, and uses its power side-channel to train a machine learning model which can be deployed to attack other identical PUFs. The experimental results show the high success of the proposed attacks even in presence of noise and temperature differences between the target PUF and the one used to train the model. We target arbiter-PUFs but we deduce that the findings extend to all its derivatives, e.g., XOR-PUFs and Feed-Forward-PUFs.

FPGA-based Physical Unclonable Functions (PUFs) have emerged as a viable alternative to permanent key storage by turning inaccuracies during the manufacturing process of a chip into a unique, FPGA-intrinsic secret. However, many fixed PUF designs may suffer from unsatisfactory statistical properties in terms of uniqueness, uniformity, and robustness. Moreover, a PUF signature may alter over time due to aging or changing operating conditions, rendering a PUF insecure in the worst case. As a remedy, we propose CHOICE, a novel class of FPGA-based PUF designs with tunable uniqueness and reliability characteristics. By the use of addressable shift registers available on an FPGA, we show that a wide configuration space for adjusting a device-specific PUF response is obtained without any sacrifice of randomness. In particular, we demonstrate the concept of address-tunable propagation delays, whereby we are able to increase or decrease the probability of obtaining 1’s in the PUF response. Experimental evaluations on a group of six 28 nm Xilinx Artix-7 FPGAs show that CHOICE PUFs provide a large range of configurations to allow a fine-tuning to an average uniqueness between 49% and 51%, while simultaneously achieving bit error rates below 1.5%, thus outperforming state-of-the-art PUF designs. Moreover, with only a single FPGA slice per PUF bit, CHOICE is one of the smallest PUF designs currently available for FPGAs.

Background: Today’s developing era data and information security plays an important role in unsecured communication between Internet of Things (IoT) elements. As the technologies are developing huge amount of information are exchanged with each other which increases the demand of a secure encryption standards. Objectives: To protect the information transmission between nodes in the perceptual layer of IoT, security is to be enhanced such that the Men in Middle (MIM) attack of information by intruders in the communication link is not possible. Methods/Statistical analysis: The security method is implemented using the concept of symmetric, asymmetric and hash algorithms between the sender and receiver. Elliptic Curve Cryptography (ECC) is performed for encrypting and sharing the Advanced Encryption Standard (AES) secret key between the sender and receiver. Elliptic Curve digital signature are added with the encrypted data for validation in transmission. Secured Hash Algorithm (SHA) is considered for generating Elliptical Curve Digital Signature Algorithm (ECDSA). All the algorithms are combined to enhance the security. Findings: Elliptic Curve Cryptography is generally applied for encrypting and sharing the secret key between the sender and receiver when Advanced Encryption Standard is used for encryption/decryption of data. A highly efficient architectures for asymmetric key encryption is applied with symmetric key encryption for encrypting the data transmitted between the devices present in the perceptual layers in the IoT. Due to security issues NIST selected SHA-3 Keccak-f[1600] algorithm. An authentication process based on ECC is applied to perceptual layer involving initialization and authentication phase apart from encryption and signature generation. Sender combines the encrypted data and key with signature together before transmitting to the receiver. The receiver verifies the signature and decrypts the key and obtains original information. Hence it is very difficult for the man in middle to access the information exchanged between the Perceptual Layer devices. Application/Improvements: This generally doesn’t require an innovative technique but an approach to develop the method implemented successfully in the perceptual layer of Internet of Things. The key is encrypted and decrypted using a novel ECC algorithm with improved ECDSA.

The Internet of Things (IoT) as an important technology consists of a heterogeneous and huge number of devices that generates an enormous amount of data in various applications. However, generating and transmitting huge amount of data in the IoT makes it crucial to implement a secure and safe data transmission scheme. Cryptography methods can secure the confidentiality, data integrity, access control, and authentication. Due to constrained resources in IoT devices, providing classical cryptography schemes isn’t efficient for IoT applications, so a lightweight cryptography scheme is one of the most important solutions to overcome security challenges in IoT. In this paper, a new security scheme called ECCCSASHA256 based on Elliptic Curve Cryptography (ECC) and Secure Hash Algorithm (SHA-256) using Crow Search Algorithm (CSA) has been proposed for secure data transmission in IoT devices. The ECCCSASHA256 model uses the CSA for generating a private key to encode the elliptic curve. Furthermore, the proposed scheme uses SHA-256 model for hashing the incoming encoded data using ECC. The simulation results indicate that the average throughput of the proposed model was about 8.22% and 8.97% higher in encryption and 8.72% and 9.81% higher in decryption compared to 3DES&amp;ECC&amp;SHA-256 and RC4&amp;ECC&amp;SHA-256, respectively.

Physically Unclonable Function (PUF) is a promising technique to enhance the security of Integrated Circuits (ICs) by providing a challenge/response pairs (CRPs) set, generated from physical properties of the device in which it is embedded. Indeed PUFs exploit small random manufacturing process variations, mainly measuring delays, to extract responses, such that they are unique and unclonable. Since PUFs are not deterministic circuits until to their realization, the test for a PUF is a process which involves statistical evaluation of some features, such as uniformity and reliability. The former measures the bits biasing for PUFs responses. The latter is related to the PUFs robustness against external uncontrolled disturbances (e.g. voltage variations), which could affect responses stability. Therefore, in this paper, we demonstrate the impact of the voltage variation on the Anderson PUF, implemented on the Xilinx Spartan-3E family. In particular, through experimental results, we show that the supplied voltage value is able to dramatically change the quality of Anderson PUF responses.