Parallel Implementation of ECC Point Multiplication on a Homogeneous Multi-Core Microcontroller

This work presents an evaluation of different software implementations of algorithms to compute the most demanding operation in cryptographic schemes based on Elliptic Curve Cryptography (ECC), the scalar multiplication. Five different methods were studied, including traditional and more sophisticated methods for elliptic curve cryptography defined over prime and binary fields. For evaluation, the key generation algorithm in ECC consisting on a single scalar multiplication was implemented on a P500h LG smarthphone, which includes an ARM processor running at 600MHz. Both execution time and memory usage was evaluated. It was found that in general, scalar multiplication runs 8 times faster for ECC defined over prime fields, being the NAF the best performer method. For ECC over binary fields, the best performer method was wNAF. The results presented in this work could help a designer to select the most appropriate method when implementing ECC-based cryptographic schemes such as encryption or digital signatures on mobile devices like smartphones, meeting implementation requirements in terms of execution time and memory usage.

The authentication of Internet of Things (IoT) devices based on the Physical Unclonable Function (PUF) is widely adopted in the information security domain. However, the leakage of PUF responses in an authentication system reduces its privacy and security. To improve its security, we can utilize the Elliptic Curve Cryptography (ECC) algorithm with different key lengths to encrypt the PUF response arbitrarily. Point multiplication is the most time-consuming operation in ECC because of its complex calculation process, which seriously affects the efficiency of the PUF response encryption. In order to solve this problem, a point multiplier based on binary field with reconfigurable key lengths of 233, 283, 409 and 571 is designed in this paper. In our method, by reusing the underlying computing units, the resources needed for point multiplication are effectively reduced. What it is more innovative is that double point multiplication operations with a key length of less than 283 bits can be performed simultaneously in the elaborate designed point multiplication circuit, which can effectively speed up the encryption process of ECC. The circuit is implemented on Xilinx Virtex-6 FPGA. The experiment results show the single point multiplication times of 233, 283, 409 and 571 key lengths are 19.33, 22.36, 41.36 and 56.5 μs, respectively, under the clock frequency of 135 MHz. In addition, it only needs 19.33 μs to perform two-point multiplication operations when the key length is 233 bits at the same time. When the key length is 283 bits, the point multiplication operation can be performed twice in 22.36 μs.

In this paper, we present an evaluation of possible ARM instruction set extension for elliptic curve cryptography (ECC) over binary finite fields GF(2/sup m/). The use of elliptic curve cryptography is becoming common in embedded domain, where its reduced key size at a security level equivalent to standard public-key methods (such as RSA) allows for power consumption savings and more efficient operation. ARM processor was selected because it is widely used for embedded system applications. We developed an ECC benchmark set with three widely used public-key algorithms: Diffie-Hellman for key exchange, digital signature algorithm, as well as El-Gamal method for encryption/decryption. We analyzed the major bottlenecks at function level and evaluated the performance improvement, when we introduce some simple architectural support in the ARM ISA. Results of our experiments show that the use of a word-level multiplication instruction over binary field allows for an average 33% reduction of the total number of dynamically executed instructions, while execution time improves by the same amount when projective coordinates are used.

This paper discusses parallelization of elliptic curve cryptography hardware accelerators using elliptic curves over binary fields F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2m</sub> . Elliptic curve point multiplication, which is the operation used in every elliptic curve cryptosystem, is hierarchical in nature, and parallelism can be utilized in different hierarchy levels as shown in many publications. However, a comprehensive analysis on the effects of parallelization has not been previously presented. This paper provides tools for evaluating the use of parallelism and shows where it should be used in order to maximize efficiency. Special attention is given for a family of curves called Koblitz curves because they offer very efficient point multiplication. A new method where the latency of point multiplication is reduced with parallel field arithmetic processors is introduced. It is shown to outperform the previously presented multiple field multiplier techniques in the cases of Koblitz curves and generic curves with fixed base points. A highly efficient general elliptic curve cryptography processor architecture is presented and analyzed. Based on this architecture and analysis on the effects of parallelization, a few designs are implemented on an Altera Stratix II field-programmable gate array (FPGA).

Elliptic curve cryptography (ECC) has shorter key length than other asymmetric cryptography algorithms such as RSA with the same security level. Existing faults in cryptographic computations can cause faulty results. If a fault occurs during encryption, false information will be sent to the destination, in which case channel error detection codes are unable to detect the fault. In this paper, we consider the error detection in elliptic curve scalar multiplication point, which is the most important operation in ECC. Our technique is based on non-linear error detection codes. We consider an algorithm for scalar multiplication point proposed by Microsoft research group. The proposed technique in our methods has less overhead for additions (36.36%) and multiplications (34.84%) in total, compared to previous works. Also, the proposed method can detect almost 100% of injected faults.

We implemented elliptic curve cryptography in the frequency domain on the MSP430 constrained microcontroller. Our implementation of 169-bit elliptic curve cryptography (ECC) on MSP430, one of the most popular microcontrollers for wireless sensor network (WSN) nodes, performs an ECC scalar point multiplication operation, for random points, in only 1.55 ms which is similar to or faster than existing implementations. To our knowledge, this work proposes the first ever software implementation of ECC in the frequency domain on a constrained low-power microcontroller.

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce&#x2019;s demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2⁵⁷¹) and GF(2²⁸³) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2⁵⁷¹), which achieves one PM operation in <inline-formula> <tex-math notation="LaTeX">$17.44~\mu s$ </tex-math></inline-formula> using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and <inline-formula> <tex-math notation="LaTeX">$12.55~\mu s$ </tex-math></inline-formula> using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2²⁸³) with the shortest computation time. It takes only <inline-formula> <tex-math notation="LaTeX">$3.21~\mu s$ </tex-math></inline-formula> to finish one PM operation on Virtex-5 and <inline-formula> <tex-math notation="LaTeX">$2.22~\mu s$ </tex-math></inline-formula> on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

Elliptic curve cryptosystems have gained increase attention and have become an intense area of research, mainly because of their shorter key length when compared to other public key cryptosystems such as RSA. Shorter key length brings advantages such as reduced computation effort, power consumption and storage requirements, making it possible to increase the available security for portable devices, smartcards and other power strained devices. ECC manages to cover all the significant cryptographic operations such as key exchange and agreement or digital signature with greater efficiency than previous systems. These operations rely heavily on point multiplication which is also the most time-consuming operation. This paper evaluates point operations (doubling, tripling, quadrupling, and addition) and proposes an algorithm for combining the operations in order to achieve faster scalar multiplication when compared to the standard algorithm for scalar multiplication of double and add.

We present a high-speed public-key cryptoprocessor that exploits three-level parallelism in Elliptic Curve Cryptography (ECC) over GF(2 n ). The proposed cryptoprocessor employs a Parallelized Modular Arithmetic Logic Unit (P-MALU) that exploits two types of different parallelism for accelerating modular operations. The sequence of scalar multiplications is also accelerated by exploiting Instruction-Level Parallelism (ILP) and processing multiple P-MALU instructions in parallel. The system is programmable and hence independent of the type of the elliptic curves and scalar multiplication algorithms. The synthesis results show that scalar multiplication of ECC over GF(2163) on a generic curve can be computed in 20 and 16 μs respectively for the binary NAF (Non-Adjacent Form) and the Montgomery method. The performance can be accelerated furthermore on a Koblitz curve and reach scalar multiplication of 12 μs with the TNAF (τ-adic NAF) method. This fast performance allows us to perform over 80,000 scalar multiplications per second and to enhance security in wireless mobile applications.

With the rapid development of cloud computing, e-commerce, authentication among multi-robot systems, the highspeed implementation of Elliptic Curve Cryptography (ECC) is in widespread use. The performance of ECC is decided by the design of scalar point multiplier, which is one of the most time-consuming component. This paper presents a full set of methods to achieve an ultra high-speed scalar point multiplier, its Scalar Point Multiplication (SPM) is optimized comprehensively in terms of speed-first design approach by concurrently implementing the Point-add (PA) and Point-double (PD) algorithms, improving large integer modular inversion algorithm and large integer modular multiplication algorithm. Finally, Montgomery domain operation and Non-Adjacent Form (NAF) encoding theory are applied to enhance the speed of scalar point multiplier. In the VLSI design, a high-speed $\pmb{256\times 256}$ -bit scalar point multiplier is achieved based on SMIC's 65nm process. It can complete single calculation of SPM within 12.5us on average, in other word, 80,000 times of SPM can be computed in one second. Compared to the scalar point multiplier realized by other publications based on VLSI, the reports for circuits synthesis show that our multiplier is optimal in terms of $AT^{2}$ and ultrafast in terms of speed.

Elliptic curve cryptography (ECC) is one of the most popular asymmetric key cryptography techniques used in secured data communications. The scalar multiplication is the most expensive operation in the ECC. In this paper, we propose a low cost hardware for scalar multiplication in Affine coordinates based ECC. Here, we use a reconfigurable Galois field (GF) arithmetic circuit, which performs various GF arithmetic operations such as addition, multiplication, inverse, and fused multiply add (FMA) using a same set of hardware circuit. Instead of using a number of multipliers and adders in point addition/doubling, we have used only one reconfigurable GF arithmetic circuit. The existing and proposed designs are implemented in 45 nm CMOS technology using Cadence. The synthesis results show that the affine co-ordinate based proposed \(GF(2^{163})\) scalar multiplier achieves \(69\%\) of reduction in the switching power dissipation as compared with the Lopez-Dahab projective co-ordinates based conventional design in 45 nm CMOS technology. KeywordsAffine coordinatesElliptic-curve cryptographyLopez-Dahab coordinatesPoint additionPoint doublingScalar multiplication

This paper introduces the ECC (Elliptic Curve Cryptography) processor, in which the τ-NAF converter and Square-Square-Add Algorithm are utilized, for point multiplication on Koblitz curves. The proposed ECC processor operates over GF(2163). The τ-NAF converter can turn the complicated point double to simple point square, and the Square-Square-Add Algorithm can decrease the number of point addition. With the proposed design, the execution time for executing point multiplication will decrease by 21%, and the AT value (Area-Time product) will be lowered by 15% than the state-of-the-art design, which achieves better efficiency on the execution of ECC over Koblitz curves.

Developing a high-speed elliptic curve cryptographic (ECC) processor that performs fast point multiplication with low hardware utilization is a crucial demand in the fields of cryptography and network security. This paper presents field-programmable gate array (FPGA) implementation of a high-speed, low-area, side-channel attacks (SCAs) resistant ECC processor over a prime field. The processor supports 256-bit point multiplication on recently recommended twisted Edwards curve, namely, Edwards25519, which is used for a high-security digital signature scheme called Edwards curve digital signature algorithm (EdDSA). The paper proposes novel hardware architectures for point addition and point doubling operations on the twisted Edwards curve, where the processor takes only 516 and 1029 clock cycles to perform each point addition and point doubling, respectively. For a 256-bit key, the proposed ECC processor performs single point multiplication in 1.48 ms, running at a maximum clock frequency of 177.7 MHz in a cycle count of 262 650 with a throughput of 173.2 kbps, utilizing only 8873 slices on the Xilinx Virtex-7 FPGA platform, where the points are represented in projective coordinates. The implemented design is time-area-efficient as it offers fast scalar multiplication with low hardware utilization without compromising the security level.

Multiplication and addition are the basic arithmetic operation used in Digital Signal Processing (DSP) for coefficient multiplication, scalar point multiplication in Elliptic Curve Cryptography (ECC) and in other fields. Multiplications are basically a shift and add operation. However, there are many different variations on how to do it. Some are more suitable to implement on FPGA than others. However time complexities and hardware complexities are the major issues in designing a multiplier unit. There are different multiplication algorithms in current technology. Hardware complexities in some design are more than time complexities whereas in some other design time complexities are more. However there must be a tradeoff between these two types of methodology. This paper will discuss a brief idea how a tradeoff can be achieved. Experimental results that have discussed here and the architecture based on the proposed algorithm shows it's novelty. Applications of the proposed algorithm on DSP and ECC have been dealt here clearly.

This paper proposes a unified, scalable dual-field Montgomery multiplier architecture which can operate in both prime GF(p) and binary extension fields GF(2n) for arbitrary prime numbers and irreducible polynomials. The Montgomery multiplier architecture has advantages in speed and flexibility for operator size compared with conventional architectures using long adders or long-bit × short-bit multipliers by introducing using a balanced r-bit×r-bit dual field multiplier. Finally, the hardware size of multipliers on GF(2n) for various r, are investigated. The Montgomery multiplier provides efficient execution of Montgomery multiplication in either field for different operand lengths, which suitable be applied to elliptic curve cryptographic (ECC) processors.