FPGA implementation of modified serial montgomery modular multiplication for 2048-bit RSA cryptosystems

Rivest, Shamir, Adleman (RSA) algorithm can be used in cryptography to send confidential messages in secure manner. RSA cryptosystem is based on modular multiplication to factorize the large integers. Montgomery modular multiplication can be used as modular multiplication because it is one of the efficient and fastest modular multiplication. Montgomery algorithm is based on add and shift operation, so Carry save adder (CSA) can be used in order to overcome the carry propagation at each addition. In this Montgomery multiplier, the CSA choses the operands and converts the addition result from carry save format to binary form. Accordingly, the architecture can use less hardware and give short critical path delay to do one modular multiplication. In this paper, the Montgomery modular multiplication uses a modified or configurable Carry save adder (CCSA). The CCSA is designed with one full adder and two half adders to reduce the delay. Still CCSA suffers from high power consumption. In order to reduce the power consumption, the full adder used in CCSA with two multiplexers has been proposed. The proposed Montgomery modular multiplier has the capability to provide 26% average reduction in power when compared with previous designs.

Secure communication is a challenging issue in modern industries and critical infrastructures. The core technology used for securing the communication is cryptography. Modular multiplication is an important operation in cryptosystems. This paper investigates a novel modular multiplication algorithm and architecture. In the proposed algorithm and architecture, the parallel architecture and compact SD technique are utilized to improve the performance of modular multiplication operation and cryptosystems. The proposed architecture is implemented on Xilinx Virtex 5 FPGA. The complexity analysis results and FPGA implementation results show that the proposed modular multiplication algorithm and architecture provide improvement on the total computation time and area×time complexity compared to other modified modular multiplication algorithms and architectures. Keyword: Security, modular multiplication architecture, FPGA, parallel computation, compact SD

Based on modified Booth's algorithm, a radix-4 cellular-array modular multiplier to fulfill the radix-4 modular multiplication algorithm is designed. We implement the modular multiplier in bit level and get rid of the extra control signals shown in by using the concept of guard bits. The radix-4 modular multiplier can be used to implement fast RSA cryptosystem. Due to reduced number of iterations and pipelining, our modular multiplier is four times faster than the cellular-array modular multiplier based on the original Montgomery's algorithm. The time to calculate a modular exponentiation is about n/sup 2/ clock cycles, where n is the word length, and the clock cycle is roughly equal to the delay time of a full adder. The utilization of the multiplier is 100% by interleaving consecutive exponentiations.

Modular multiplication is the fundamental operation in most public-key cryptosystem. Therefore, the efficiency of modular multiplication directly affects the efficiency of whole crypto-system. This paper presents implementation and comparison of several recently proposed, highly efficient architectures for modular multiplication on FPGAs: interleaved multiplication, two variants of Montgomery multiplication, Jeong-Burleson multiplication, multiplication based on key size partitioning and complement. Finally, new hardware architecture for time optimal modular multiplication is proposed based on Hamming weight and position of one's in multiplicand.

Cloud computing is a technology that provides secure storage space for the customer’s massive data and gives them the facility to retrieve and transmit their data efficiently through a secure network in which encryption and decryption algorithms are being deployed. In cloud computation, data processing, storage, and transmission can be done through laptops and mobile devices. Data Storing in cloud facilities is expanding each day and data is the most significant asset of clients. The important concern with the transmission of information to the cloud is security because there is no perceivability of the client’s data. They have to be dependent on cloud service providers for assurance of the platform’s security. Data security and privacy issues reduce the progression of cloud computing and add complexity. Nowadays; most of the data that is stored on cloud servers is in the form of images and photographs, which is a very confidential form of data that requires secured transmission. In this research work, a public key cryptosystem is being implemented to store, retrieve and transmit information in cloud computation through a modified Rivest-Shamir-Adleman (RSA) algorithm for the encryption and decryption of data. The implementation of a modified RSA algorithm results guaranteed the security of data in the cloud environment. To enhance the user data security level, a neural network is used for user authentication and recognition. Moreover; the proposed technique develops the performance of detection as a loss function of the bounding box. The Faster Region-Based Convolutional Neural Network (Faster R-CNN) gets trained on images to identify authorized users with an accuracy of 99.9% on training.

본 논문에서는 Montgomery 알고리즘을 기반으로 시스톨릭 어레이 구조를 이용한 효율적인 Radix-4 모듈러 곱셈기 구조를 제안한다. 제안된 알고리즘을 이용하여 모듈러 곱셈을 위한 반복의 수가 감소되었으며, 따라서 n-비트의 모듈러 곱셈을 수행하기 위하여 (3/2)n+2 클럭이 소요된다. 그러나 하드웨어의 이용도를 감안할 때 두 개의 곱셈에 대한 중첩(interleaving) 연산이 가능하며, 가장 빠른 시기에 새로운 곱셈을 시작한다면 하나의 모듈러 곱셈을 수행하기 위하여 평균 n/2 클럭이 필요하다. 제안된 구조는 시스톨릭 어레이 구조의 잇점으로 규칙성과 확장성을 갖기 때문에 효율적인 VLSI 구조로 설계하기가 용이하다. 기존의 다른 구조들과 비교하여 볼 때 제안된 구조는 상대적으로 적은 하드웨어들을 사용하여 높은 수행 속도를 보여주었다. In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery's algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n+2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n/2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.

Modular multiplication is a crucial operation in public-key cryptography systems such as RSA and ECC. In this study, we analyze and improve the iteration steps of the classic Montgomery modular multiplication (MMM) algorithm and propose an interleaved pipeline (IP) structure, which meets the high-performance and low-cost requirements for Internet of Things devices. Compared to the classic pipeline structure, the IP does not require a multiplexing processing element (PE), which helps shorten the data path of intermediate results. We further introduce a disruption in the critical path to complete an iterative step of the MMM algorithm in two clock cycles. Our proposed hardware architecture is implemented on Xilinx Virtex-7 Series FPGA, using DSP48E1, to realize the multiplier. The implemented results show that the modular multiplication of 1024 bits by 2048 bits requires 1.03 μs and 2.13 μs, respectively. Moreover, our area–time–product analysis reveals a favorable outcome compared to the state-of-the-art designs across a 1024-bit and 2048-bit modulus.

Modular exponentiation of large number is widely applied in public-key cryptosystem, also the bottleneck in the computation of public-key algorithm. Modular multiplication is the key calculation in modular exponentiation. An improved Montgomery algorithm is utilized to achieve modular multiplication and converted into systolic array to increase the running frequency. A high efficiency fast modular exponentiation structure is developed to bring the best out of the modular multiplication module and enhance the ability of defending timing attacks and power attacks. For 1024-bit key operands, the design can be run at 170MHz and finish a modular exponentiation in 4,402,374 clock cycles.

Modular exponentiation in a finite field is the basic computation involved in most public key crypto systems, such as Diffie-Hellman key exchange, ElGamal, etc. The current paper presents a new parallel architecture whereby the modular multiplication and squaring can be processed simultaneously in GF(2m) in m clock cycles using a cellular automata. Since the proposed cellular automata architecture is simple, regular, modular, cascadable, it can also be utilized efficiently for the implementation of VLSI.

Large integer modular multiplication and modular addition/subtraction are basic operations in elliptic curve cryptography (ECC). Traditionally, systolic array was used to implement modular multiplication. It is not efficient because of data dependency between neighbor processing elements (PEs). In this paper, we propose a compact modular multiplication and addition unit (MMAU) specific for ECC by dividing an improved Montgomery modular multiplication (MMM) algorithm into three parts, mapping them correspondingly to a 3-stage pipelined circuit and adding a small amount of hardware to the third stage of the pipeline for implementing modular addition/subtraction without affecting the performance of MMM. The MMAU computes one modular multiplication and one modular addition/subtraction in every 3(n+7) clock cycles for n-bit operands. When the pipeline is fully utilized, the MMAU can generate a result at every n+7 cycles. The experimental results show that our scheme achieves a higher throughput with less resource compared with existed ones.

High-radix Montgomery Modular Multiplication (MMM) is flexible and consumes fewer cycles, but turns inefficient especially when it comes to low-bit calculation. In this brief, we propose a high-radix MMM algorithm, called Separated Iterative Digit-Digit Modular Multiplication (S-IDDMM), which accelerates the MMM by taking full advantage of multipliers and adders. The relationship among clock cycles, pipeline of multiplications and number of multipliers for the proposed algorithm is derived and utilized to optimize the overall efficiency jointly. Xilinx Virtex-7 FPGA implementations of S-IDDMM in 256 bits and 512 bits are constructed with radix-32 and radix-64, respectively. Compared with IDDMM design reported elsewhere (Amiet et al., 2016), our calculation time is reduced by more than 2 times with a similar area cost, due to deep use of multipliers and higher frequency.

The HyperElliptic Curve Cryptosystem (HECC) was quite extensively studied during the recent years. In the open literature one can find results on how to improve the group operations of HECC as well as teh implementations for various types of processors. There have also been some efforts to implement HECC on hardware devices, like for instance FPGAs. Only one of these works, however, deals with the inversion-free formulae to compute the group operations of HECC. We present inversion-free group operations for the HEC y2 + xy = x5 + f1x + f0 and we target characteristic-two fields. The reason is that of allowing a fair comparison with hardware architectures using the affine case presented in [BBWP04]. In the main part of the paper we use these results to investigate various hardware architectures for a HECC VLSI coprocessor. If area constraints are not considered, scalar multiplication can be performed in 19,769 clock cycles using three field multipliers (of type D = 32), one field adder and one field squarer, where D indicates the digit-size of the multiplier. However, the optimal solution in terms of latency and area uses two multipliers (of type D = 4), one addition and one squaring. The main finding of the present contribution is that coprocessors based on the inversion-free formulae should be preferred compared to those using group operations containing inversion. This holds despite the fact that one field inversion in the affine HECC group operation is traded by up to 24 field multiplications in the inversion-free case.

Latch and flip-flop design in QCA technology with minimum number of cells

Elliptic Curve Cryptography (ECC) is considered a more effective public-key cryptographic algorithm in some scenarios, because it uses shorter key sizes while providing a considerable level of security. Modular multiplication constitutes the “arithmetic foundation” of modern public-key cryptography such as ECC. In this paper, we propose the Cascade Operand Scanning for Specific Modulus (SMCOS) vectorization method to speed up the prime field multiplication of ECC on Single Instruction Multiple Data (SIMD) architecture. Two key features of our design sharply reduce the number of instructions. 1) SMCOS uses operands based on non-redundant representation to perform a “trimmed” Cascade Operand Scanning (COS) multiplication, which minimizes the cost of multiplication and other instructions. 2) One round of fast vector reduction is designed to replace the conventional Montgomery reduction, which consumes less instructions for reducing intermediate results of multiplication. Further more, we offer a general method for pipelining vector instructions on ARM NEON platforms. By this means, the prime field multiplication of ECC using the SMCOS method reaches an ever-fastest execution speed on 32-bit ARM NEON platforms. Detailed benchmark results show that the proposed SMCOS method performs modular multiplication of NIST P192, Secp256k1, and Numsp256d1 within only 205, 310 and 306 clock cycles respectively, which are roughly 32% faster than the Multiplicand Reduction method, and about 47% faster than the Coarsely Integrated Cascade Operand Scanning method.

Modular multiplication is the fundamental operation in Elliptic Curve Cryptography (ECC) and a multitude of hardware implementations have been developed so far. In this paper, a series of modifications to a high performance radix-2 interleaved modular multiplication architecture are proposed. The design was implemented on a Virtex-7 FPGA for five prime fields recommended for ECC by the National Institute of Standards and Technology (NIST), showing a significant improvement in area-time efficiency in comparison to the original architecture.