From behavioral description to systolic array based architectures

소프트웨어의 취약성을 검증하기 위하여 소프트웨어의 구조를 유추하여 유추된 구조를 활용하여 테스트하는 방법이 주목받고 있다. 이와 같은 방법을 사용하기 위해서 효과적인 소프트웨어의 구조 유추 방법이 요구된다. 많이 사용되는 DFG(Data Flow Graph), CFG(Control Flow Graph) 이나 CFA(Control Flow Automata)와 같은 그래프나 트리 방식은 소프트웨어 모델을 구조적으로 표현하지 못하는 단점을 가진다. 본 논문에서는 이러한 단점을 극복할 수 있는 방법을 제시한다. 제시된 방법은 바이너리 코드에 다양한 입력데이터 들을 부여하여 입력데이터별 CFG를 생성하고, 생성된 CFG들이 구조적으로 표현될 수 있도록 계층적 제어 흐름 그래프(Hierarchical Control Flow Graph, HCFG)를 작성한다. 또한 제안하는 HCFG을 생성하는데 요구되는 그래프의 구성요소와 점진적 그래프 생성 알고리듬도 제시한다. 제안한 방법론을 공개된 SMTP(Simple Mail Transfer Protocol) 서버 프로그램에 적용시켜 소프트웨어의 모델을 작성하는 실험을 수행하고, 생성된 모델과 실제 소프트웨어 구조를 비교 분석한다. To verify software vulnerability, the method of conjecturing software structure and then testing the software based on the conjectured structure has been highlighted. To utilize the method, an efficient way to conjecture software structure is required. The popular graph and tree methods such as DFG(Data Flow Graph), CFG(Control Flow Graph) and CFA(Control Flow Automata) have a serious drawback. That is, they cannot express software in a hierarchical fashion. In this paper, we propose a method to overcome the drawback. The proposed method applies various input data to a binary code, generate CFG's based on the code output and construct a HCFG (Hierarchical Control Flow Graph) to express the generated CFG's in a hierarchical structure. The components required for HCFG and progressive algorithm to construct HCFG are also proposed. The proposed method is verified through constructing the software architecture of an open SMTP(Simple Mail Transfer Protocol) server program. The structure generated by the proposed method and the real program structure are compared and analyzed.

This paper presents a novel methodology for automated parallel exploration of datapath and Unrolling Factor (UF) in High Level Synthesis (HLS) using hyper-dimensional particle encoding based swarm intelligence (termed as ‘H-SI’) for control and data flow graphs (CDFGs). The major novel contributions of the proposed approach are as follows: (a) Hybrid design space exploration (DSE) framework that concurrently balances the tradeoff between the following: i) conflicting metrics of power - execution time ii) control states and execution delay during loop unrolling iii) orthogonal condition of enhancing Quality of Results (QoR) and reducing the exploration runtime; (b) automated parallel exploration of data path and loop UF through an integrated hyper-dimensional particle encoding approach using swarm intelligence; (c) power model for evaluation of design points during exploration; (d) model for estimation of execution delay of a loop unrolled CDFG (for any UF value) based on an available resource without necessity of tediously unrolling the entire CDFG in most cases. Results indicated an average improvement in QoR of >38 % and reduction in runtime of > 93 % compared to recent approaches.

This paper explores the problem of identifying malicious code sections in applications for the Android. A method for analyzing Android applications is proposed, based on applying of static analysis using control flow graphs and data flow graphs. The paper formally describes the dependency relationships that are used to construct graphs, and also describes an algorithm that allows to identify malicious sections of code using the received graphs. The results of an experimental evaluation of the effectiveness of the proposed method are presented, demonstrated a high probability of detecting malicious portions of the code of Android applications.

Large Language Models (LLMs) have gained traction in domains from software development to cybersecurity, particularly for detecting vulnerabilities in program source code. Their ability to analyze large codebases and identify security weaknesses makes them valuable in software security analysis. However, their effectiveness declines in the absence of intermediate representations such as Abstract Syntax Trees (AST), Control Flow Graphs (CFG), and Data Flow Graphs (DFG), or even tokenized forms of code. In this research study, we assess the performance of LLMs in detecting vulnerabilities directly from raw source code, without structural representations. By designing context-specific prompts, we aim to enhance the model's understanding of code semantics. Our findings show that LLMs can partially identify vulnerabilities from raw code alone, reaching up to 43% accuracy. This indicate both the potential and current limitations of prompt-based LLMs for static vulnerability detection.

BGNN4VD: Constructing Bidirectional Graph Neural-Network for Vulnerability Detection

An Ameliorated Methodology for the Abstraction of Object Oriented Features from Software Requirements Specification

Current software defect prediction and code quality assessment methods treat these inherently related tasks independently, failing to leverage their complementary information. Existing graph-based approaches lack the ability to jointly model structural dependencies and quality characteristics, limiting their effectiveness in capturing the complex relationships between defect patterns and code quality indicators. This paper proposes a novel integrated model that simultaneously tackles both objectives using graph neural networks to leverage the inherent graph structure of software systems. Our novelty lies in the first-of-its-kind integration of multi-level graph representations (AST, CFG, DFG) with a dual-branch attention-based GNN architecture for simultaneous defect prediction and quality assessment. Our approach constructs multi-level graph representations by integrating abstract syntax trees, control flow graphs, and data flow graphs, capturing both syntactic and semantic relationships in source code. The proposed dual-branch GNN architecture employs shared representation learning with attention mechanisms and multi-task optimization to exploit complementary information between defect prediction and quality assessment tasks. Comprehensive experiments on six real-world software projects demonstrate significant improvements over traditional methods, achieving F1-scores of 0.811 and AUC values of 0.896 for defect prediction, while showing 9.3% average improvement in code quality assessment accuracy across multiple quality dimensions. The integration strategy proves effective in capturing complex structural dependencies and provides actionable insights for software development teams, establishing a foundation for intelligent software engineering tools that deliver comprehensive code analysis capabilities.

In this paper an optimum algorithm to translate control flow graphs to dataflow graphs is proposed for dataflow execution of sequential programs. Some of the existing analysis methods restrict the specification of a program to be processed while others require a very high analysis cost. The algorithm proposed in this paper (CD translation algorithm), (1) with a very low cost, and (2) for any control structure that can be described by a control flow graph, (3) can generate dataflow programs that give an optimum dataflow execution. Furthermore, this proposed analysis algorithm is designed to handle task level control flow graphs as well as instruction level control flow graphs, which are accepted by the existing methods, so that optimum control is possible for task level dataflow execution.

Automatic vectorization is crucial for improving the performance of computationally intensive programs. Existing compilers use conservative optimization strategies for automatic vectorization, which, in many cases, lead to the loss of vectorization opportunity. Studies have shown that the use of machine learning algorithms to build a performance prediction model is beneficial to improve the program performance. The model input is program features, and the output is the predicted optimization strategies or the program performance related to the optimization. In this paper, we focus on a computational intensive loop structure-tensor contraction, which is common in quantum chemical simulations. Most existing machine learning methods rely on control and data flow graphs as features to represent programs, but different tensor contraction kernels have the same control and data flow graphs. In addition, the existing methods often use the same kind of learning algorithm to construct a learning model, which is prone to overfitting and low-precision problems. In this paper, we propose an automatic vectorization performance enhancement method based on ensemble learning. We construct an ensemble learning model to predict the performance of tensor contraction kernels with different vectorization strategies and select the best vectorization strategy for the kernels. According to the storage access patterns of the tensor contraction kernels, we propose a static method for features representation. Based on the multi-algorithm ensemble learning strategy, we obtain better learning results than the single learning algorithm. The experimental results show that the prediction model achieves 88% and 87% prediction efficiency on two different platforms with different instruction sets, data types, and compilers. Compared with the existing methods, the prediction efficiency is greatly improved. In addition, the average peak performance is $2.96 \times $ of Intel ICC 12.0 and $2.98 \times $ of GCC 4.6 compiler, respectively.

Behavioral synthesis is the task of refining a behavioral description into a Register Transfer Level (RTL) description through a set of successive transformations. The two main models used during this refinement process are the internal representation of the behavioral description, and the target architecture. The internal representation, also called intermediate form, fixes the underlying design model of the behavioral synthesis tool (see CFG, DFG or CDFG further). The choice of this model constitutes one of the main decisions when building a behavioral synthesis tool. Although intermediate forms are generally not accessible to the users of such tools, their understanding may help to better comprehend the functioning of the tool. The target architecture is generally composed of a datapath and a controller; when fixed, it also fixes the performances of the synthesized design. The understanding of the target architecture is particularly important in order to evaluate and debug the result of behavioral synthesis.

Many data-driven software engineering tasks such as discovering programming patterns, mining API specifications, etc., perform source code analysis over control flow graphs (CFGs) at scale. Analyzing millions of CFGs can be expensive and performance of the analysis heavily depends on the underlying CFG traversal strategy. State-of-the-art analysis frameworks use a fixed traversal strategy. We argue that a single traversal strategy does not fit all kinds of analyses and CFGs and propose bespoke control flow analysis (BCFA). Given a control flow analysis (CFA) and a large number of CFGs, BCFA selects the most efficient traversal strategy for each CFG. BCFA extracts a set of properties of the CFA by analyzing the code of the CFA and combines it with properties of the CFG, such as branching factor and cyclicity, for selecting the optimal traversal strategy. We have implemented BCFA in Boa, and evaluated BCFA using a set of representative static analyses that mainly involve traversing CFGs and two large datasets containing 287 thousand and 162 million CFGs. Our results show that BCFA can speedup the large scale analyses by 1%-28%. Further, BCFA has low overheads; less than 0.2%, and low misprediction rate; less than 0.01%.

Integer Linear Programming (ILP) is commonly used in high level and system level synthesis. It is an NP-Complete problem (in general cases). There exists some tools that give an optimal solution for small ILP formulations. Nevertheless, these tools may not give solutions for complex formulations. In this paper, we present a solution to overcome the problem of complexity in ILP formulations. We propose a partitioning methodology based on a constraint graph representing all the constraints included in any ILP formulation. To direct the partitioning, the constraint graph nodes are grouped to represent Data Flow Graph (DFG) nodes. This reduced constraint graph can be used to partition any ILP formulation based on DFG. We illustrate this method on ILP formulation for scheduling. Results on ILP scheduling formulations are promising.

The paper presents an approach to reduce interconnect cost by insertion of identity operations in a control and data flow graph (CDFG). Other than previous approaches, it is based on systematic pattern analysis and automated transformation selection. The cost function controlling transformation selection is derived with statistical experiments and is optimized using practical benchmarks. The results show significantly reduced interconnect cost for most register architectures and application examples.

In high-level synthesis, a data flow graph (DFG) description of an algorithm is mapped onto a register transfer level description of an architecture. Each node of the DFG is scheduled to a specific time and allocated to a processor. In this paper, we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with automatic retiming, pipelining, and unfolding while performing module selection and dataformat conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a processor optimal schedule. During module selection an appropriate processor is chosen from a library of processors to construct a cost optimal architecture. Furthermore, we also include the cost and latency of data format conversions between processors of different implementation styles. We also present a new formulation for minimizing the unfolding factor of the blocked schedule. The approach presented in this paper is the only systematic approach proposed so far to include implicit unfolding and to perform synthesis using nonuniform processor styles and data format converters.

An autonomous navigation agent needs to learn the navigation rules and the transition among different navigation states, which can be summarized in Turing Machine (TM) controlled by a navigation Finite Automata. However, real-world inputs to this TM is always noisy with numerous appearance variances and distractors, which made it impossible to handcraft symbolic representations or features to detect. Developmental Network-l (DN-1) incrementally learns a Finite Automata error-free using emergent representation but lacks hierarchy in its internal representation. In this paper, we extend DN-1 by adding lateral connection and multiple types of neurons to form hierarchical representation both internally and in the motor area. The formed hierarchical representation is more robust against distractors compared to the global feature patches in DN-1. Compared to other FA based methods, DN-2 directly uses natural input without handcrafting. The navigation states are emergent from the firing patterns in network areas instead of the hand-crafted symbolic states in the neural network output layer. Real-world and simulated navigation experiments showed that DN-2 successfully approximated rules of navigation using natural inputs. The agent learns different levels of concepts from simple to complex with the help of internal hierarchical representation.