From Design to Test: A High-Speed PRBS

Pseudo random bit sequence (PRBS) generation is important for a wide range of applications including communication systems, pattern generation and encryption. All optical pseudo random bit sequence (PRBS) generation using both regular and quantum dot (QD) semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer have been studied. The speed of operation is limited by the gain and phase recovery times in the SOA. A key element in the fabrication of a PRBS generator is an all optical XOR. All optical XOR functionality has been demonstrated experimentally using regular semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer at 80 Gb/s. The performance of the XOR operation has been analyzed by solving the rate equation of the SOA for SOAs with both regular and QD active region. QD-SOAs should result in significantly higher speed operation. The paper shows that QD-SOA based devices can be used to produce PRBS generators that operate near 250 Gb/s.

There is a close relationship between encryption and randomness. The security of encryption algorithms usually depends on the random choice of keys and bit sequences. A famous example is Shannon’s result. Ciphers with perfect secrecy require randomly chosen key strings, which are of the same length as the encrypted message. In Chapter 9, we will study the classical Shannon approach to provable security, together with more recent notions of security. One main problem is that truly random bit sequences of sufficient length are not available in most practical situations. Therefore, one works with pseudorandom bit sequences. They appear to be random, but actually they are generated by an algorithm. Such algorithms are called pseudorandom bit generators. They output, given a short random input value (called the seed), a long pseudorandom bit sequence. Classical techniques for the generation of pseudorandom bits or numbers (see [Knuth98]) yield well-distributed sequences. Therefore, they are well-suited for Monte Carlo simulations. However, they are often cryptographically insecure. For example, in linear congruential pseudorandom number generators or linear feedback shift registers (see, e.g., [MenOorVan96]), the secret parameters and hence the complete pseudorandom sequence can be efficiently computed from a small number of outputs.

Security and privacy problems in communication systems and social media platforms where digital image/video are shared almost always, have attracted researchers interest on information security. Starting from this point of view, a novel one-dimensional chaotic maps based pseudo random bit generator is proposed to make a significant contribution to the literature about protection of personal data in any network. Electronic circuit realizations of Logistic and Tent maps as entropy source are designed on Orcad-Pspice environment and state variables are inputted to novel post-processor algorithm. The rest of main blocks of proposed pseudo random bit generator design are built up fixed-point binary conversion algorithm, XOR processor and H function post-processor. The generated pseudo random bit series are tested by using NIST 800.22 statistical test suite and applied to color image encryption in order to show the effectiveness of proposed design. Cryptanalysis processes such as histogram, NPCR-UACI and correlation analysis are demonstrated. Analysis results show that the proposed design can be used successfully in many secure communication and media transmission applications.

In this paper, we propose a wideband signal reconstruction scheme for testing high-speed pseudo random bit sequences (PRBSs) in the presence of jitter noise using incoherent sampling. The proposed approach exploits synchronous multirate sampling (SMRS) hardware and multicoset back-end signal processing algorithms. The SMRS hardware consists of multiple analog-to-digital converters (ADCs) whose sampling frequencies are synchronized with a common frequency reference and can be individually configured. The optimal sampling frequency of each ADC is chosen based on the input signal information and sampling hardware specifications. As compared to other sampling hardware used for multicoset signal reconstruction, the proposed approach uses less number of ADCs and does not require accurate sampling clock phase adjustment. In the digital signal reconstruction, the input waveform is reconstructed by the multicoset signal processing algorithms and the phase noise of each tone of the PRBS test signal is measured.

Linear feedback shift registers (LFSRs) are essential components of communications systems such as pseudo random bit sequence (PRBS) generators, convolutional encoders, scramblers and randomizers [1, 2]. Fig.1 (left) shows a LFSR scheme in which the XOR gate is operated among two tapped bits i and i+k within the shift register. The result bit is fed to the shift register at the last position (n) and the sequence in the register is 1-bit shifted as well. The experimental setup for demonstrating an all-optical LFSR is shown in Fig.1 (middle). The main components of the scheme are an optical buffer [3], a bit selecting circuit, and a XOR gate. The data vector (A) is generated by modulating the continuous wave (CW) λ s with a 10Gbps non-return-to-zero (NRZ) electrical pattern whose period is T P =33.3168µs. Only 5 bits are used as the initial sequence for the shift register. The travelling time of the packet in the buffer is T L =1.85 µs, meaning that up to 18 round trips can be accommodated by the pattern's period T P but one of those should be preserved for erasing the buffer before it is fetched a new sequence. The initial sequence enters the buffer as well as propagates directly to the bit selecting circuit. Every round trip, a new sequence as a replica of the previous one plus the feedback bit comes out. At the last round trip, a pump signal inserted into the buffer through the circulator will strongly reduce the gain of the semiconductor optical amplifier (SOA). Both the circulating packet and the accumulating in-band amplified spontaneous emission (ASE) noise will be suppressed. The buffer is now completely cleaned for a new cycle. The first and the last bits of the 1-bit shifted sequence are selected for the XOR operation. Referring to Fig.1 (left), i=1 and k=4, n=5. With this setup, the bit selecting circuit requires 2 clock signals (C) for tap the proper bits from the incoming sequence. The sampling process is done by exploiting four-wave-mixing (FWM) in a 250m-long highly nonlinear fiber (HNLF). Since at every round trip the sequence must be 1-bit shifted, the sampling clocks must be accordingly delayed for 1 bit, resulting the clock period of T C =T L +T B where T B =100ps is the bit time. The outputs of the bit selecting circuit are fed as pump signals to port a and d of a SOA Mach Zehnder interferometer (MZI). They are synchronized with a clock at λ s used as the probe signal (F) at port b. The output of the XOR gate is then fed back into the buffer. The feedback bit should be precisely allocated at the end of the packet circulating inside the buffer, meaning that the feedback time should be T F =T L +T B +T seq in which T seq is the original sequence duration and equal to 500ps in our setup. Fig.1 (right) depicts the results at the 10th round trip for two different input initial sequences (10001) and (10011) taken at point (B). The equalization between bits in the sequence and the quality of the pulses is strongly limited by the accumulating ASE noise inside the buffer, the long fiber-based structure and the bit's polarization. The fiber-based setup also causes misalignment between the clocks, spoils the essential synchronism and degrades the performance of the FWM and the XOR operation. One possible solution for solving all of these problems and hence improving the performance is the integration approach. The bit selection could be implemented exploiting nonlinear effects into an SOA or a periodic-poled lithium niobate (PPLN) instead of using a long HLNF. Moreover the extinction ratio of the pulses at the SOA-MZI XOR output (<13.5dB) could be improved, e.g. with a saturable absorber at its output, thus increasing the number of allowed round trips into the shift register and reducing the noise on the final bit sequence.

This paper describes the architecture and design of 2.5Gb/s non-PLL-type all-digital clock recovery circuit. The proposed circuit is non-PLL-type and designed in fully digital style to provide faster acquisition time and better scalability and portability. Output jitter would not be accumulated since the proposed circuit recovers output clock for every transition of input data. Furthermore, it can recover the final output clock from potential candidate clock signals without any special elaborated techniques and the acquisition time is fast enough. The proposed circuit is designed using 130nm, 1.2V CMOS technology and simulated for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1 pseudo random bit sequence data at 2.5Gb/s with HSpice circuit simulator. The phase shifts in recovered clock for input data skew is within ±40ps, and peak-to-peak jitter and RMS jitter are 49ps and 4.5ps, respectively.

We demonstrated 40 GHz all-optical clock recovery system using an erbium-doped fiber laser that incorporates a 10 GHz electro-absorption modulator and a linear optical amplifier. We successful recovered 40 GHz clock signals from a 40 Gb/s pseudo random bit sequences. Stable pulses with pulsewidth of 6 ps and timing jitter of 300 fs are obtained.

In this paper, we propose and demonstrate a low-complexity fiber nonlinearity impairments compensation (NLC) scheme based on simple recurrent neural network (SRNN), combining with the triplets derived from the first-order perturbation solution of the coupled nonlinear Schrodinger equation. Benefitting from the time memory of SRNN, the proposed NLC can reduce the computational complexity without sacrificing the compensation performance compared with the schemes based on memoryless feedforward neural networks. To verify the feasibility of the proposed NLC, the simulation systems of single channel and three channel 30 GBaud polarization division multiplexing (PDM) 16 quadrature amplitude modulation (QAM) over 2400 km standard single mode fiber transmission are constructed respectively. Comprehensive numerical simulation results demonstrate that although the NLC performance of proposed scheme is inferior to that of digital back propagation (DBP) with much higher complexity and impracticality, it can still achieve the competitive NLC performance with lower computational complexity compared to the schemes based on deep neural network (DNN) and artificial neural network (ANN). Moreover, it is further proved that using triplets as the feature required for NLC can cause the pattern of pseudo random bit sequence to be destroyed, resulting in the neural network-based NLC scheme not suffering from the problem of overestimation for performance. Additionally, the time memory of SRNN enables the number of triplets in training set required by the SRNN-based NLC to be reduced by 169% compared to that of DNN and ANN. The experimental results of 16 GBaud PDM-16QAM wavelength division multiplexing coherent systems demonstrate that compared to with ANN and DNN, the comparable NLC performance can also be achieved by the proposed scheme with lower complexity.

A novel method to combine encryption and channel coding in such a way as to get increased security without any additional complexity is presented in this paper. A secure communication system usually consists of an encryption block followed by the channel coder. The encryption block here is a Shrinking generator which is a Linear Feedback Shift Register (LFSR) based stream cipher system. The channel coding technique used is Turbo codes or Low Density Parity Check Codes (LDPC) that performs very well and provides results near Shannon's Limit. Controlled randomness using Pseudo Random Bit Sequence (PRBS) generator is incorporated during encoding of these codes to provide additional level of security in the system without any additional complexity. To achieve optimum decoding, soft decision decoding algorithms are used rather than hard decisions. Bit Error Rate (BER) performance of the proposed channel coders with keyed randomness is well analyzed for intended and un-intended users. Security of the system is analyzed by mounting Improved Linear Consistency Attack and the results show that a significant increase in security is achieved in a stream cipher based secure communication system without any additional increase in complexity by introducing security in channel coding.

본 논문에서는 다중점 위상검출기(Phase detector: PD)를 이용한 1Gbps 클럭 및 데이터 복원(Clock and data recovery: CDR)회로를 제안한다. 제안된 위상검출기는 데이터의 천이 모서리와 클럭의 상승/하강 모서리 3점을 비교하여 up/down 신호를 생성한다. 기존의 위상검출기 회로는 클럭 주기의 배수 만큼의 up/down 펄스폭을 갖는 출력으로 전압제어발진기(Voltage controlled oscillator: VCO)를 조절하는 펄스폭변조(Pulse width modulation: PWM)방식을 사용한다. 제안된 위상검출기 회로는 클럭 반주기만큼의 up/down 펄스폭을 갖는 출력으로 전압제어발진기를 조절하는 펄스수변조(Pulse number modulation: PNM)방식을 사용하여, 전압제어발진기를 미세하게 조절함으로써 지터를 줄일 수 있다. 제안된 위상검출기를 이용한 클럭 및 데이터 복원회로는 1Gbps의 전송률을 갖는 231-1개의 랜덤 데이터를 이용하여 테스트되었고, 지터와 전력소비는 각각 7.36ps와 12mW로 저전력, 적은 지터의 특징을 보였다. 제안된 회로는 0.18um CMOS 공정에서 1.8V 전원으로 설계되었다. The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps <TEX>$2^{31}-1$</TEX> pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

Volterra kernels are well known to be the multidimensional extension of the impulse response of a linear time invariant (LTI) system. It can be used to accurately model weakly nonlinear, specifically, polynomial nonlinearity systems. It has been used in the past for white-box model order reduction (MOR) to model frequency-domain performance metric quantities such as distortion in power amplifiers (PA). In this paper, we train a neural network from time-domain response of high-speed link buffers to extract multiple high-order kernels at once. Once the kernels are extracted, they can fully characterize the dynamics of the buffers of interest. Using the kernels, we demonstrate that time-domain response is straight-forward to obtain using super-, or multi-dimensional convolution. Previous work has used a shallow feed-forward neural network to train the system by using Gaussian noise as the identification signal. This is not convenient for the method to be compatible with existing computer-aided design tools. In this work, we directly use a pseudo random bit sequence (PRBS) to train the network. The proposed technique is more challenging because the PRBS has flat regions which have highly rich frequency spectrum and requires longer memory length, but allows the method to be compatible with existing simulation programs. We investigate different topologies including feed-forward neural network and recurrent neural network. Comparisons between training phase, inference phase, convergence are presented using different neural network topologies. The paper presents a numerical example using a 28Gbps data rate PAM4 transceiver to validate the proposed method against traditional simulation methods such as IBIS or SPICE level simulation for comparison in speed and accuracy. Using Volterra kernels promises a novel way to perform accurate nonlinear circuit simulation in the LTI system framework which is already well known and well developed. It can be conveniently incorporated into existing EDA frameworks.

A high-speed optical interface circuit for 850-nm optical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18-mum 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simulations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed-responsivity tradeoff. Due to the lower responsivity, a very sensitive transimpedance amplifier is needed. At 500 Mb/s, an input power of -8 dBm is sufficient to have a bit error rate of 3middot10-10. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and modified Cherry-Hooper stage is analyzed. To achieve broadband operation in the output buffer, so-called fT doublers are used. For a differential 10 mVpp 231-1 pseudo random bit sequence, a bit error rate of 5middot10-12 at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mVpp input signal results in a bit error rate of 7middot10-14. The TIA consumes 17mW, while the post-amplifier circuit consumes 34 mW

High-bandwidth single-mode selectively oxidized vertical-cavity surface-emitting laser (VCSEL) arrays operate at 980 nm or 850 nm emission wavelength for substrate or epitaxial side emission. Coplanar feeding lines and polyimide passivation are used to reduce electrical parasitics in top-emitting GaAs and bottom-emitting InGaAs VCSELs. To enhance fundamental single-mode emission for larger devices of reduced series resistance a surface relief transverse mode filter is employed. Fabricated VCSELs are applied in various interconnect schemes. InGaAs quantum-well based VCSELs at 935 nm emission wavelength are investigated for use in perfluorinated graded-index plastic-optical fiber (GI-POF) links. We obtain a 7 Gb/s pseudo random bit sequence (PRBS) nonreturn-to-zero (NRZ) data transmission over 80 m long 155 /spl mu/m diameter GI-POF. We investigate data transmission over standard 1300 nm, 9 /spl mu/m core diameter single-mode fiber with selectively oxidized single-mode GaAs and InGaAs VCSELs. We achieve biased 3 Gb/s and bias-free 1 Gb/s pseudo-random data transmission over 4.3 km at 830 nm emission wavelength where a simple fiber mode filter is used to suppress intermodal dispersion caused by the second order fiber mode. For the first time, we demonstrate 12.5 Gb/s data rate transmission of PRBS signals over 100 m graded-index multimode fiber or 1 km single-mode fiber using high performance single-mode GaAs VCSELs of 12.3 GHz modulation bandwidth emitting at /spl lambda/=850 nm.

Time delay estimation between two phase shifted signals via generalized cross-correlation methods

In this paper, a novel pseudo random bit generator is presented. It exhibits better inviolability properties, with respect to the traditional one, and it can be efficiently used in cryptography applications where high security is required. The proposed circuit is based on the classical linear feedback shift register (LFSR) with the feedback network dynamically modified. It has been evaluated with the most common randomness tests, giving excellent results. Moreover, the main statistical properties of the novel generator have been compared with those of a LFSR of equivalent length. The results have shown an equivalent performance of the circuits under comparison.