Fully Integrated Discrete-Time Superheterodyne Receiver in Nano-Scale CMOS

New methods are proposed to implement the exclusive-OR and exclusive-NOR functions at the transistor level under low supply voltage. Since the dynamic power dissipation in CMOS is proportional to V/sub dd//sup 2/, low-voltage operation of the circuit is an important issue. The main design objectives for these new circuits are low power dissipation and full-voltage swing at a low supply voltage (V/sub dd/=2 V). The proposed designs are compared with previously known circuits and are shown to provide superior performance. Several XOR circuits have been fully simulated using HSPICE with a 0.4 /spl mu/m CMOS technology at 2 V supply voltage.

We propose a technique to use dual supply voltages in digital designs to reduce energy consumption. New algorithms are proposed for finding and assigning a lower voltage in a dual voltage design. Given a circuit and a supply voltage and an upper bound on the critical path delay, the first algorithm finds an optimal lower supply voltage and a second algorithm assigns that lower voltage to selected gates. A linear time algorithm described in the literature is used for computing slacks for all gates of the circuit for a given supply voltage. For the computed gate slacks and the lower supply voltage, all gates are divided into three groups such that no gate in the first group can be assigned the lower supply, all gates in the second group can be simultaneously set to lower supply while maintaining positive slack for every gate, and gates in the third group are assigned low voltage, iteratively, in selected subsets at a time. The gate slacks are recalculated after each such voltage assignment. Thus, the overall complexity of this reduced power dual voltage assignment procedure is O(n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). SPICE simulations of ISCAS'85 benchmark circuits using the 90-nm bulk CMOS technology results show up to 60% energy savings.

This paper proposes a hybrid class-AB/class-B voltage-controlled oscillator (VCO) with low voltage, low power, and a wide tuning range. The class-AB VCO core is designed to ensure robust start-up of the class-B VCO core. Featuring a high-efficiency class-B VCO core, the combination of class-AB/class-B VCO cores consumes low dc power. Based on the proposed architecture, the fabricated 0.18-μm CMOS VCO exhibits a measured tuning range of 25.6%. Operating at a low supply voltage of 0.75 V, the hybrid class-AB/class-B VCO cores consume a low total dc power of 2.4 mW. In this bias condition, the measured average value of phase noise for all frequency ranges is -101.4 dBc/Hz at 1-MHz offset from the carriers. Compared to recently published wide-tuning range VCOs, the proposed hybrid class-AB/class-B VCO simultaneously achieves a low supply voltage, a low dc power dissipation, and wide tuning range, leading to a good figure-of-merit including the tuning range (FOMT). In addition, the theories for analyzing the VCO are given in detail, and the mechanisms are validated by experiments.

Nowadays IC designers are constantly challenged not only with single-chip integration but also with low-voltage and low-power designs. This is motivated both by the increasing demand of low-voltage low-power IC designs from most market segments and by the reliability concern under voltage scaling of deep-submicron CMOS processes. While many low-voltage RF circuits [SHA 97, WAN 98, WON 02] have been able to operate at very low supply voltages, and recently low-voltage receiver front-end [UGA 01] has been demonstrated with special SIMOX/CMOS processes of low VT, the possibility of integrating 1-V channel-select filter and A/D converter in a CMOS process with high-VT is still unknown.

A low-voltage and low-power down-conversion bulk-driven mixer using standard 0.13 mum CMOS technology is presented in this letter. To work on a low supply voltage and low power consumption applications while maintaining reasonable performance, the bulk-driven technique is selected in this V-band mixer design. The mixer has a conversion gain of 0 plusmn1.5 dB from 51 to 65 GHz with low supply voltage of 1 V and low power consumption of 3 mW. To our knowledge, the MMIC is the highest frequency CMOS bulk-driven mixer to date with good conversion gain and low power consumption among the recently published active mixers around 60 GHz.

The probability of timing failure in SRAM accessing becomes unacceptably high at low voltages, which makes the SRAM become the bottleneck of the system performance. Recently proposed timing speculation SRAM (SSRAM) can access bit cells much earlier than the conservative time margin and detect the potential timing failures. Unfortunately, the performance benefit brought by this speculative scheme might be nullified by the extra cycles used to correct the errors. Therefore, in a cache architecture, cachelines containing bit cells with timing failure bring significant performance degradation in a low-voltage scenario. In this paper, we propose the set-associative L1 and L2 Remapping and Reuse-aware timing Speculation caches (RRS caches) based on the cross-sensing SSRAM to reduce the weak cacheline access penalties under low supply voltages. RRS caches improve the proportion of the error-free cachelines (or strong cachelines) by clustering as more as possible bit cells with timing failures into weak cachelines. In addition, RRS caches swap the frequently reused data to the error-free cachelines to further reduce the average access latency and the energy consumption by an optimized filling/replacement policy. We compared the performance, energy consumption and area overhead of RRS caches with those of state-of-the-art approaches. According to our simulation results, RRS caches improve the system performance close to that of the Perfect caches in a four-core processor with only 0.12% extra energy consumption, 4.12% extra area overhead in the L1 cache and 2.69% extra energy consumption, 5.66% extra area overhead in the L2 cache compared to the cache designs with the raw SSRAM.

Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nanoscale CMOS LC oscillators.

Technology scaling is leading to supply voltage reduction and shrinking voltage headroom, making it very challenging for analog circuits to achieve high signal-to-noise-and-distortion ratios (SNDRs). For example, at Vdd ≤ 0.6V, the peak signal swing is 30% of Vdd in [1]-[3]. Since timing accuracy is improving in nanoscale CMOS, techniques have been proposed representing analog information in the time or phase domain. However, the linearity of the transformation between time or phase domain and the voltage or current domain remains a bottleneck at low supply voltages. In [2], ring-oscillator based integrators replace conventional OTA-based integrators, but the output signal swing is still limited to 30% of Vdd by the voltage headroom of the charge pump, which performs phase-to-voltage conversion. We propose switched-mode signal processing where analog information is represented in terms of pulse widths at the amplifier output stage, which can be replaced with power-efficient rail-to-rail class-D stages, thus producing switched-mode operational amplifiers (SMOAs). We present a 0.6V 70MHz 4th-order continuous-time Butterworth filter designed with SMOAs that achieves a dynamic range of 58dB, an SNR of 55.8dB and a THD of 60dB at +2.8dBm output signal power, while dissipating 26.2mW.

Multi-band RF front-ends with adaptive image rejection : a DECT/Bluetooth study case

This paper discussed the design of a fast acquisition frequency synthesizer for frequency hopping CDMA in the 2.4 GHz band. The frequency synthesizer can make channel switching within one microsecond while operating at 3 V. In order to achieve fast acquisition, low phase noise and low harmonic content under very low supply voltage, specially designed voltage controlled oscillator, frequency doubler and switchable loop filter were adopted for optimum performance. Measurements on the prototype showed that the acquisition time was 0.79 /spl mu/s. The proposed design is suitable for the low voltage and low power handheld equipment. With minor modification, the design can be applied to other digital cellular applications, such as DCS-1800 handsets.

The automatic amplitude control (AAC) loop is an indispensable element for the practical realization of VCOs embedded in a complete transceiver. Its noise however can unacceptably degrade the single-sideband-to-carrier ratio (SSCR) performance of the oscillator, this problem being even exacerbated in low-voltage circuits. This paper addresses the design issues of a low-voltage low-noise differential LC-VCO with AAC, tunable within a 2.3-2.8-GHz frequency range, fully integrated in bipolar technology with 2-V power supply. First, the mechanisms through which the AAC noise affects the output phase are identified as the poor indirect stability and the AM-to-PM conversion due to the varactors. The effect of the AAC noise is discussed and substantially reduced with suitable design choices. We show that the achievable noise-to-signal ratio is bounded by the shot noise coming from the bias source of the differential oscillator, an intrinsic limit set by the low supply voltage which does not allow for degeneration of the tail transistor. Second, the design of the AAC is discussed. A large gain-bandwidth product (GBWP), about 100 MHz, has been implemented in order to correct for the fast oscillation amplitude variations and reduce the effect of the ground line disturbances. The expected value of the phase noise level, SSCR at 100 kHz =-104 dBc/Hz, is tightly matched by the experimental results. The core oscillator dissipates 7 mA, while less than 600 /spl mu/A are drawn by the AAC circuit.

A frequency-tuning negative-conductance (-G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) boosted structure and applications for a voltage-controlled oscillator (VCO) is presented in this paper. Analog tuning varactors connected to a -G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> boosted structure is proposed to significantly alleviate the limitation of the tuning range for the -G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> boosted structure, resulting in a low-voltage low-power wide-tuning-range VCO. Based on the proposed architecture, the fabricated 0.18-μm CMOS VCO exhibits a measured 49.8% tuning range. Operating at 0.65 V low supply voltage, the VCO core consumes 2.37-mW dc power. At this bias condition, the measured average value of phase noise for all frequency ranges is -115.1 dBc/Hz at 1-MHz offset from the carriers. Relative to recently published wide-tuning-range CMOS VCOs, the proposed VCO simultaneously achieves low supply voltage, low dc power dissipation, low phase noise, and a wide tuning range, leading to a good figure-of-merit (FOM) and FOM including the tuning range. Furthermore, formulas of analysis for the proposed frequency-tuning -Gm boosted structure and wide VCO tuning range are presented, and the mechanisms are validated by experiments.

In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The oscillator is realized in digital 65-nm CMOS as a dual-core LC-tank oscillator based on a high-swing class-C topology. It is tunable within 4.07–4.91 GHz, while drawing 39–59 mA from a 2.15 V power supply. The measured PN is $-$ 146.7 dBc/Hz and $-$ 163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it the lowest reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance is not critical even with a 1% mismatch between the cores. This approach can be extended to a higher number of cores and achieve an arbitrary reduction in PN at the cost of the power and area.

International audience

In the paper, we present a design of a low voltage Operation Amplifier (OPAMP) circuit using split-length transistors. Indirect feedback compensation is an advanced technique used to stabilize the operation of an OPAMP. Cascode transistors are usually implemented for indirect feedback systems. However, these transistors are not suitable for low voltage design. In this study, we have taken advantage of split-length transistors and indirect feedback compensation technique to design a high performance OPAMP. As a result, the OPAMP operates not only at low supply voltage but also at high frequency. The OPAMP has been designed and fabricated in a 0.18um CMOS technology. This OPAMP achieves 100 dB gain, 90 MHz unity gain frequency and 60 degrees phase margin at 2 V supply voltage.