Future wireless convergence platforms

In the past, radio systems were designed to communicate using one or two wave forms. As a result, two groups of people with different types of traditional radio were not able to communicate due to incompatibility. The need to communicate with people using different types of equipment can only be solved by using software defined radio (SDR). SDR is a wireless device that works with any communication system, be it a cellular phone, a pager, a WI-FI transceiver an AM or FM radio, a satellite communications etc. In both hardware and software Digital Signal Processing (DSP) techniques are used to design a real time system. For SDR applications involving high complexity, it becomes impossible to stay with single sampling rate and so altering the sampling rate at different stages is required for low cost DSP hardware. Thus variable sampling rates i.e. Multirate Digital Signal Processing is required.

Software Defined Radios (SDRs) are wireless communication systems in which many of the radios' important functional elements, including filtering, frequency translation and modulation/demodulation, are implemented in software via Digital Signal Processing (DSP) techniques using embedded processors and Field Programmable Gate Arrays (FPGA) as described by Harris and Lowdermilk in 2010 [1]. SDRs differ from traditional radios that typically employ custom silicon to implement such functions. SDRs exhibit several advantages over traditional radios, including re-configurability and reduced development costs and time-to-market since they do not require custom silicon. SDRs also enjoy long life cycles, since they can readily be adapted to meet future needs. Cognitive Radios (CRs) are a special class of SDRs that employ adaptive DSP technologies to implement spectral management. This enables CRs to deliver improved effective bandwidth, quality of service, and enhanced security, which have become increasingly important in modern commercial and military wireless communications applications.

Since the initiation of the Joint Tactical Radio System (JTRS) program, the concept of software defined radio (SDR) has received considerable attention and significant progress has been made. While the raison d'etre of SDR is somewhat different for military and commercial applications, they share similar challenges in implementing a true SDR. A true SDR faces numerous hardware and software challenges, many of them still to be addressed by research. In the literature concerning SDR software architecture and requirements, the technology requirements tend to be sidelined. This is mainly because, in the JTRS program, the focus is on voice and low data rate applications; also, the frequency band is limited to UHF. On the other hand, the implementation cost is less of a concern for now. However, by the emergence of advance warfare technology where it is required to transport more bits per warrior to accommodate video and telemetry data, and also by introducing initiatives similar to the JTRS to other communication systems, the technology requirements of SDR have to be revisited. The paper focuses on the hardware technology aspect of SDR. The main technical objective of SDR is a versatile reconfigurable platform, which provides interoperability. The main blocks of a true SDR are: intelligent antenna; programmable RF modules; high-performance digital-to-analog (DAC) and analog-to-digital converters (ADC); digital signal processing (DSP) techniques/technology; interconnection technology.

It is expected that multiple radio access standards and systems will coexist in the same environment beyond 3G. The superior re-configurability and re-programmability of software-defined radio (SDR) had made itself become the most promising technology to realize such a flexible radio system. Several research projects have involved in the development of SDR systems, but their efforts mainly focus on hardware design. A software framework that allows users, manufactures or operators to insert, remove, update and configure protocols, applications and hardware modules is also an essential part of a SDR system. Unfortunately, current commercial operating systems (OS) lack of fully supports of SDR features. In this paper, the impacts of SDR on the OS and the extension of the OS for a SDR system are investigated. Moreover, the design and implementation of a software framework based on a commercial on-the-shelf (COTS) OS are also presented.

Efficient and effective broadband wireless technologies are required to support the foreseeable need to process and exchange large amounts of data. In this Special Issue of the Springer Journal of Signal Processing Systems various disciplines of such efficiency and effectiveness in the context of Software-Defined Radio (SDR) technologies are discussed. At first, a selection of articles focuses on “spectral efficiency”. Since frequency spectrum is known to be scarce and limited, it becomes a resource of increasing value whose utilization must be handled with care. The rapidly growing demand for higher data throughputs in wireless communication does not allow inefficient use of spectrum anymore. Two promising approaches to tackle the “spectral efficiency” issue are Cognitive Radio (CR) and Dynamic Spectrum Access (DSA). A Cognitive Radio is capable of learning and adapting to its transmission environment. Taking e.g. spectrum sensing results into account, the decisions for accessing the scarce frequency spectrum in the most flexible and effective manner are made. CRs are typically based on SDR technology. Thus, the first set of articles puts emphasis on topics in the areas of Cognitive Radio, Cognitive Radio Networks, and Spectrum Sensing. The second selection of articles addresses the problems of “energy efficiency” and “implementation efficiency”. Especially in wireless communications these types of efficiencies are highly important to increase battery time of modern SDRbased platforms. The architectures of such SDRs are typically based on heterogeneous multi-processor hardware platforms hosting General Purpose Processors (GPP), Digital Signal Processors (DSP), Field Programmable Gate Arrays (FPGA) and sometimes even more specific processing elements. Each type of processor has a specific advantage in one or the other performance criterion like energy consumption, flexibility, processing time, throughput, waveform portability, components reusability etc. Whenever a new waveform shall be implemented on an SDR, the system designer has to take the decision for the best possible trade-off between all of these, partly conflicting, criteria under the given circumstances. For instance, the portability of waveform components can be improved by fulfilling the constraints of the Software Communications Architecture (SCA) specification and by using common Application Programming Interfaces (API). Thus, the second set of articles puts particular emphasis on topics in the areas of SDR and SCA Implementations.

The ultimate objective of Software Defined Radio (SDR) is to replace the entire analog signal processing in the wireless transceivers with digital signal processing. This will provide the flexibility, through reconfiguration or reprogramming, to enable the transceivers to work with different air-interfaces standards using a single generic hardware platform. Most of the research in SDR to date has been focused on base stations, which do not have as tight constraints in size and power consumption as handsets. However, in order to realize the promise of integrated services and global roaming capabilities, the design and development of a multi-standard SDR handset with dynamic reconfigurability is crucial. The size and power constraints imposed by handsets with limited resources pose a major design challenge. This special issue brings together 11 papers that address various aspects of this challenge from the perspectives of wireless systems, computing architectures, embedded systems and signal processing. The most important part of an SDR transceiver is the wideband analog-to-digital converter (ADC) that converts the radio frequency signal received by the antenna into digital form for further processing. The first paper, “A multi-mode sigma-delta ADC for GSM/WCDMA/WLAN applications” by Jose et. al. proposed a cascaded reconfigurable sigma-delta modulator that is able to work with three different communication standards. This design, implemented in 0.18 μm CMOS technology, exhibits excellent signal-to-noise plus distortion ratios and has reduced power consumption compared to conventional designs. After ADC, the digitized received signal will need to be separated into signals within the various bands specified by the communication standard. This is performed by the channelizer which has the highest computational requirements of the whole SDR system. The second paper, by Panicker et al., reviews the state-of-the-art filter bank channelizer techniques with low power and dynamic reconfigurability properties. The design of reconfigurable devices can be optimized using the methodology of parametrization which bring together the common aspects of a myriad number of wireless standards into a single processing procedure. In this way, the implementation of the multi-standard SDR will be greatly simplified. “Promising technique of parametrisation for reconfigurable radio, the Common Operators Technique: fundamentals and examples” by Alaus et al. presents the common operator technique for parametrization which is less standards dependent than the more conventional Common Function technique. The direct digitization of the radio frequency (RF) signal requires very high speed ADCs which is not readily available using current technology. Therefore, current SDR implementations typically down-converts the RF A. P. Vinod (*) School of Computer Engineering, Nanyang Technological University, Nanyang, Singapore e-mail: asvinod@ntu.edu.sg

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

A software-defined Radio (SDR) is a wireless communication system whose main radio functionalities are implemented in software on an embedded system instead of hardware. The advantages of SDR include its wide range of frequency channels that have configurable bandwidths in addition to its support of multiple configurations and modulations. In this paper, an SDR bridge implemented within a wireless sensor network (WSN) is developed. The SDR bridge is inserted as a gateway between sensor nodes and the end-user receiver to add security to the overall network. For this study, LoRa link is chosen to ensure communication between the network components because of its low power consumption and its long range. Typically, the sensor nodes will send their data to the SDR bridge using LoRa modulation. The bridge will add a layer of security to the overall system by encrypting the signals sent within the bridge. Experimental results found during this study showed that the SDR Bridge allows successful interconnection of the sensor nodes and the end-user receiver. Also, the SDR Bridge prevented reception of the data by the user when data was encrypted unless the proper key was used. Encryption of the signal did not have a significant effect on the QoS since the Packet Loss Ratio (PLR) of the link was around 1.6%. When the bridge is used, the Received Signal Strength Indication (RSSI) was also within the typical values for the LoRa receiver.

Software Defined Radio (SDR) has evolved in the past decade from a topic that was only briefly mentioned in passing in graduate special topics courses to one that is now accessible to students at all levels. The rapid proliferation of cost effective SDR hardware has allowed not only the development of undergraduate SDR communication labs, but affordable test instrumentation that may be used in a variety of courses. This paper will outline a series of hardware choices and exercises that make SDR not just a topic for advanced communications, but a topic that can enhance undergraduate and graduate courses in communications, analog and digital signal processing, and instrumentation.

Software Defined Radio (SDR) or Software Radio is one of the most important technologies for the modern wireless communication system. SDR is a radio which can tune to any frequency band, implement different modulation and demodulation schemes and different standards in the same device by using reconfigurable hardware and powerful software. SDR provides flexible, upgradeable, multi-standard and longer lifetime radio equipment for both the military and for civilian wireless communications infrastructure. This paper provides a detailed analysis of SDR hardware and its operation focusing on analog front end and digital front end. The paper also highlights the benefits of SDR. However, it was expected to implement SDR since the third generation of wireless communication but many practical challenges that SDR faces, causing SDR evolution slower. This paper also discusses some of the current issues impacting the SDR technology and investigates how they are being resolved.

The new Xilinx Early-Access Partial-Reconfiguration (EAPR) FPGA technology exhibits a clear advantage over the former modular-based partial-reconfiguration flow. This paper compares a Handel-C implementation of the two approaches, demonstrating the limitations of the old method, which are fully addressed by the EAPR. It is argued here that the combination of Handel-C and EAPR offers a viable approach towards realization of the future Software Defined Radio (SDR) systems. Two EAPR-based SDR architectures are presented, which trade off complexity for reconfiguration speed. Finally a cost-efficient, fast mode-switching architecture, particularly suitable for Time Division Duplex (TDD) radio systems is presented. The proposed architecture utilizes this property to dynamically reconfigure the transmission and reception chain algorithms at different times.

"Radio Design in Nanometer Technologies" addresses current trends and future directions in radio design for wireless applications. As radio transceivers constitute the major bottleneck in a wireless chipset in terms of power consumption and die size, the radio must be designed in the context of the entire system, end to end. Therefore the book will address wireless systems as well as the DSP parts before it gets into coverage of radio design issues. To that end, the book contains three parts: Part 1 is a general part discussing current and future wireless networks, chipset evolution over the past decade and ending with a discussion on radio requirements for software defined radio(SDR). Part 2 will focus on the digital baseband of a wireless chip set, flexible DSP cores for multi-standard wireless platforms and system-on-chip SoC implementation and design flow issues. Part 3 will be devoted to radio design issues starting at the transceiver level and going down to discuss critical issues facing design of future multi band multi standard radios for emerging wireless standards such as UMTS, WiMaX, MIMO and WLAN in a way that is consistent with the prevailing vision of SDR. As such, the book is the first volume that looks at the integrated radio design problem as a 'piece of a big puzzle', namely the entire chipset or single chip that builds an entire wireless system. This is the only way to successfully design radios to meet the stringent demands of today's increasingly complex wireless systems

We summarize the security necessary for software defined radio (SDR) systems, and propose a flexible structure for security systems on SDR. We introduce a new electronic commerce scheme for SDR that utilizes the ability of SDR to switch between different security algorithms for electronic commerce. We evaluate the performance of the cryptographic algorithms used in electronic commerce on various platforms including SDR systems, as basic research toward the implementation of SDR.

this paper reviews the state of the technique of field programmable gate array (FPGA) for partial Reconfiguration (PR), design methodologies of Wireless Communication System, such as Multi Carrier Code Division Multiple Access (MC-CDMA) technique has been to be suited for future wireless systems that are expected to provide higher data rates and greater flexibility for the services of voice, data, video and Internet to the users due to its property in using the bandwidth in efficient manner. The Software Defined Radio is considered as a wireless system applied by routines so as software. Consequently, the use of SDR allows vehicle manufacturers to familiarize communication applications sustained through cars to appropriate to the standards of the respected country presented in the object oriented programming. FPGAs are playing a very significant role in SDR. However, in modern wireless communication system programs, SDR and CR need to design a wide range of waveforms complex, which it is complicated in design and performance and implementation needs more time. The design of the modulation and demodulation and other signal processing application of PR technique that have the ability to modify blocks of logic dynamically by downloading partial bit files, while the remaining logic is still working without interruption; thus, power consumption and configuration time can be saved for a larger extent. The PR using was allowed to move for fewer or smaller devices as, decrease power and increase system upgradability.

For conventional wireless transceiver architectures with software-defined radio (SDR) technology, the communication between microcontrollers, DSPs (digital signal processors), and memories are through public shared buses. As wireless standards change frequently, the demands of bus bandwidth increase. To avoid bus bottlenecks and to get better performance, the wireless transceiver architectures with concatenate memories and concatenate buses are proposed. The application-specific instruction-set processor (ASIP) for the IEEE 802.11p standard and the electronic system-level (ESL) virtual platform for the inner receiver of IEEE 802.11p are built. Via the proposed transceiver architectures with concatenate memories and concatenate buses, the bandwidth of communication between DSPs through public shared buses can be saved because the communications between DSPs and concatenate memories are through concatenate buses.