Gate sizing: a general purpose optimization approach

: This thesis considers two problems in computer-aided design of VLSI circuits: (1) discrete gate sizing and (2) timing-driven placement improvement. The discrete gate-sizing problem is described as follows. A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient solution algorithm for combinational circuits, we examine the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification. This is done by appropriately selecting a size for each gate in the circuit and by adjusting the delays between the central clock distribution node and individual flip-flops. Existing methods treat these two problems separately, which may lead to very suboptimal solutions in some cases. We develop a novel unified approach to tackle them simultaneously. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.

Segmentation of clusters by template rotation expectation maximization

The authors are concerned with the optimisation of combinational logic circuits. The competing factors, active area and delay time, are considered in the optimisation. The total active area is assumed to be a linear function of the gate sizes. There is a critical path whose delay time, the longest delay time of the circuit, depends on the sizes of the individual gates. This path will change many times during the optimisation. The optimisation process is used to produce the trade-off curve. The proposed methodology is based on the optimisation of the circuit critical path. This is a gate sizing problem on those paths that define the delay time of a circuit. Given a drive size for all the gates of the circuit, the trade-off curve contains design space points of minimum delay time and active area. A variable-sized subset of the Boolean network is optimised. Only the gates in the circuit critical path are optimised. The gates in the Boolean network which are not in the critical path do not need to be optimised. An efficient method is proposed for updating the critical path as the trade-off curve is obtained. Performance comparison and results were obtained over the set of MCNC two-level and combinational multilevel benchmark circuits. The proposed methodology produces trade-off curves, in relatively large circuits, with a great reduction in number of variables and run-time compared with the original full problem. In the proposed method, the number of variables is reduced by a factor of up to 7.3 times relative to the original full problem. The run-time behaviour is excellent, with an improvement between 1.5 and 32.5 times less CPU time compared with computation of the full Boolean network. With a higher gate count of the circuit, there are greater improvements in both run-time and number of variables.

Increasing dominance of process variations in the nanometer designs are posing significant challenges for circuit design and optimization. The variations in parameters such as channel length and the gate oxide thickness impacts circuit delay and power. In this paper, we propose a new gate sizing algorithm using fuzzy mathematical programming (FMP) in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay, which is a function of gate sizes and the fan-outs of the gate, are represented using triangular fuzzy numbers with linear membership functions. The variation aware gate sizing problem is formulated as a fuzzy mathematical program to perform a delay constrained power minimization in the presence of variations. Initially, a deterministic optimization is performed by fixing the fuzzy parameters to the worst and the average case values and the results are used to convert the fuzzy optimization problem into a crisp non-linear problem which is then solved using a non-linear optimization solver. The above model with delay and power as constraints, maximizes the robustness, i.e., the variation resistance of the circuit and thus the yield. The proposed approach was tested on ISCAS '85 benchmarks and the results were validated for timing yield using monte-carlo simulations. The fuzzy approach yields significantly better results compared to stochastic programming based gate sizing approach with a comparable runtime.

We consider the problem of circuit partitioning for multiple-chip implementations. One motivation for studying this problem is the current need for good partitioning tools for implementing a circuit on multiple field programmable gate array (FPGA) chips. We allow duplication of logic gates as it could be used to reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin constraints on each chip, using the general delay model. We develop a repeated network cut technique for finding a cluster that is bounded by both area and pin constraints. Our algorithm achieves optimal delay under either the area constraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the nonoptimality occurs, and we show that the condition rarely occurs in practice. We tested our algorithm on a set of benchmark circuits, and consistently obtained optimal or near-optimal delays.

We consider the problem of circuit partitioning for multiple-chip implementation. One motivation for studying this problem is the current needs of good partitioning tools for implementing a circuit on multiple FPGA chips. We allow duplication of logic gates as if would reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin constraints on each chip, using the general delay model. We develop a repeated network cut technique for finding a cluster that is bounded by both area and pin constraints. Our algorithm achieves optimal delay under either the area constraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the non-optimality occurs and show that the condition occurs rarely in practice. We tested our algorithm on a set of benchmark circuits and consistently obtained optimal or near-optimal delays. >

The trends in technology scaling have made nanometer designs highly susceptible to reliability threats like soft errors and crosstalk noise while uncertainty in process parameters have made the physical realization of devices and interconnects unpredictable. The limitations in manufacturing processes and the impact of environmental noise poses a major threat to the signal quality, and hence the realization of reliable, low-power, high performance designs with acceptable parametric yields is a challenging problem. Most noise analysis and prevention techniques reported in the literature target single noise sources. However, reliability issues like crosstalk noise and radiation induced soft errors are deeply inter-related. Further, manufacturing variations have decreased the efficacy of online detection and correction schemes used for traditional noise optimization. In this work, we have proposed a methodology for simultaneous optimization of soft error rate(SER), crosstalk noise and power of circuits with delay constraints under process variations. Soft errors are modeled using a novel first order analysis model while crosstalk noise is modeled at the logic level using clustering based on Rent's exponent. The proposed multi-metric gate sizing methodology have been formulated into a mathematical program and has been efficiently solved. Experimental results on ISCAS'85 benchmark circuits indicate significant improvements in SER, crosstalk noise and timing yield compared to the corresponding constrained optimization problems.

The interconnect temperature of very large scale integration (VLSI) circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. The method is based on the logical effort delay model. The minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The analytical formulation of the method takes into account the maximum input capacitance, the load to be driven, and the given timing constraint. Electrical simulations show that the proposed method is very precise for a first order approach, as it presents small average errors of 1.48% in power dissipation, 2.28% in delay propagation, and 6.5% in transistor sizes.

The well-studied gate-sizing optimization is a major contributor to IC power-performance tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of constraints, scale to large circuits, and effectively utilize a large (but finite) number of possible gate configurations, including Vt and Lg. Within the research-oriented infrastructure used in the ISPD 2012 Gate Sizing Contest, we develop a metaheuristic approach to gate sizing that integrates timing and power optimization, and handles several types of constraints. Our solutions are evaluated using a rigorous protocol that computes circuit delay with Synopsys PrimeTime. Our implementation Trident outperforms the best-reported results on all but one of the ISPD 2012 benchmarks. Compared to the 2012 contest winner, we further reduce leakage power by an average of 43%.

We introduce a new gate sizing rule for significantly improving the speed performance of static logic paths designed in submicron CMOS technology. This methodology is based on the definition of local gate sizing criterion. It is directly deduced from analytical models of the output transition time and of the short circuit power dissipation, which are validated on a 0.18 /spl mu/m CMOS process. This sizing methodology is shown to offer a low power implementation alternative that can be used as an initial solution, prior to any logic path optimization.

In this article, we derive a simple and accurate expression for the change in timing yield due to a change in the gate delay distribution. It is based on analytical bounds that we have derived for the moments of the circuit and path delay. Based on this, we propose computationally efficient algorithms for (1) discrete gate sizing and (2) simultaneous gate sizing and threshold voltage ( V T ) assignment so that the circuit meets a timing yield specification under parameter variations. The use of this analytical yield gradient within a gradient-based timing yield optimization algorithm results in a significant improvement in the runtime as compared to the numerical method, while achieving the same final yield. It also allows us to explore a larger search space in each iteration more efficiently, which is required in the case of simultaneous resizing and V T assignment. We also propose heuristics for resizing/changing the V T of multiple gates in each iteration. This makes it possible to optimize the timing yield for large circuits. Results on ITC ’99 benchmarks show that the proposed multinode resizing algorithm results in a significant improvement in the runtime with a marginal average area penalty and no cost to the final yield achieved.

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.

Chapter 24 - GPU-Based Parallel Computing for Fast Circuit Optimization

Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%.