GPU-Friendly FRW Algorithms for Electrostatic Computation Problems

Due to the advantages on scalability and reliability, the floating random walk (FRW) algorithm has been widely adopted for calculating the capacitances among three-dimensional (3-D) conductors. This is evidenced by the industrial practice of interconnect capacitance extraction during the design of high-performance very large-scale integrated (VLSI) circuits. In this work, the FRW algorithm is enhanced through the distributed parallel computing. With an efficient and adaptive task allocation scheme, the communication among different computer nodes is largely reduced. A distributed algorithm for accelerating the space management is also proposed. They have been implemented with Message Passing Interface (MPI) and applied to the high-precision capacitance simulation for touchscreen design and the interconnect capacitance extraction of VLSI circuits. Experiments on a computer cluster show that the proposed techniques achieve up to 114X speedup while using 120 cores, and build up the space management structure for a VLSI case including two million conductor blocks in just 22 seconds (37X parallel speedup on 60 cores).

Fault detection and diagnosis are critical challenges in Very Large Scale Integration (VLSI) circuits, where even minor defects can cause significant performance degradation or system failure. Traditional fault detection methods often struggle with scalability and real-time analysis as circuits grow increasingly complex. This paper proposes an AI-augmented framework that leverages machine learning algorithms and neural networks to enhance the fault detection process in VLSI circuits. The proposed model not only identifies and classifies faults with high accuracy but also provides root-cause diagnostics, significantly reducing testing time and maintenance costs. Simulation results demonstrate the effectiveness of the AI-based approach in comparison with conventional techniques, showcasing improved fault coverage, faster detection, and scalability for modern chip designs. This study serves as a step toward the integration of intelligent diagnostics into chip manufacturing, paving the way for more robust and self-healing electronic systems.

The non-Manhattan conductor geometry existing in some capacitance extraction problems brings difficulty to the floating random walk (FRW) method using cubic transition domains. In this chapter, techniques are presented to enhance the FRW method for handling the structures with non-Manhattan conductors. Based on the aligned-box distances and corresponding calculating approaches, the techniques for generating the Gaussian surface and constructing axis-aligned transition cubes are presented. A practical strategy is then presented to judge the domination relationship of non-Manhattan conductor blocks for building the space management structure with candidate list. Finally, the strategy using rotated transition cube and related space management technique are presented to make further acceleration. Experiments on three-dimensional (3-D) interconnect structures including from eight to one thousand non-Manhattan blocks show that the developed method is from 2.9X to 96X faster than a simple extension of the original FRW method. The developed FRW solver is also up to 39X faster than a boundary element method based solver. Additional experiments are carried out to further validate the accuracy and efficiency of the presented techniques, and to demonstrate their suitability for large and multi-dielectric structures.

During the development of a VLSI (Very Large Scale Integration) circuits; their internal stress due to packaging combined with local self heating becomes serious and may result in large performance variation, circuit malfunction and even chip cracking. Surface peaks thermal detection is necessary in large VLSI circuits. This paper presents a VLSI circuit thermal stress monitoring approach using surface peak thermal detector algorithm and GDS (Gradient Direction Sensors) method. The design of surface peak thermal detector algorithm (SPTDA) with flexible modular-based architecture will be presented. Several approaches were implemented to achieve a better performance for the SPTDA algorithm operation. A parallel processing strategy is used to minimize computational delay. Furthermore, a hardware-efficient factoring approach for calculating tangent and division functions required by SPTDA algorithm is used to minimize silicon space in regards of their implementation. Description of the algorithm developed for the surface peaks thermal detection and the architecture implementation results are reported and compared with finite element method (FEM) temperature computations.

Capacitance extraction for interconnect parasitics modeling is the basis of accurate circuit simulation and physical verification for quality integrated circuit (IC) design. Due to its scalability and reliability, the floating random walk (FRW) based solver has been widely used for the capacitance extraction. In this paper, the recently developed techniques on distributed parallel FRW solver and for handling complex floating metals are presented. With them, the efficiency and accuracy of capacitance extraction/simulation for very large-scale integration (VLSI) circuit design are remarkably improved.

This paper presents techniques that use macromodels in order to extend and improve the floating random walk (FRW) method for capacitance extraction. A macromodel is built for each sub-structure for which it is necessary or convenient to hide its geometry details during capacitance extraction. Then, a macromodel-aware random walk scheme connects the Markovchain random walk inside the macromodels and the FRW outside through scalable blank patch regions. This method can be used for instance to extract capacitances for structure with encrypted sub-structures, and extend the FRW method's capability for structure with complex geometry or repeated layout patterns. Numerical results validate the merits of the proposed method with structures including encrypted FinFET layout, complex geometry features, and cyclic layout patterns.

Very large scale Integration (VLSI) was used to create hardware which initiates by the explanation of algorithm as well as employs computer program. In digital systems, multiplier and adder are the fundamental components in design of integrated circuit applications. High speed devices play an essential role in VLSI applications. Adder enhancement is used in miscellaneous application in new VLSI system like multiplier design, ALU and etc. An efficient adder circuit design is used to optimize various metrics. But, design complexity was not reduced by existing VLSI design. To handle such limitations, Deep Fully Connectedness Convolutional Broken Stick Regressive Brent-Kung Adder Enhancement (DFCCBSRBKAE) Technique is introduced in VLSI circuits. Input layer, two hidden layers as well as output layer comprises four layer of DFCCBSRBKAE Technique. The carry inputs are transferred to input layer. Input data is transferred to hidden layer 1. Broken-stick regression analysis is performed for pre-processing data. Next, pre-processed data is transferred to hidden layer 2. Carry generation and post-processing is carried out in hidden layer 2 and the output results are covered by the convolution. At last, outcomes were attained within output layer. This in turn helps to perform an efficient adder enhancement of digital multiplier with minimal power and time consumption. The performance of DFCCBSRBKAE Technique is determined by power and time consumption. DFCCBSRBKAE Technique reduces the area, speed, and delay and power consumption of adder enhancement compared with conventional methods.

Routing is a crucial stage in the physical design of Very Large Scale Integration (VLSI) circuits, comprising three phases: global routing, track assignment routing, and detailed routing. With the development of VLSI circuits, scholars have proposed various track assignment routing algorithms. However, improving the efficiency of track assignment routing and optimizing conflicting design rules have become bottlenecks in track assignment routing problems. This study addresses these bottlenecks by utilizing single-level horizontal and vertical Steiner trees to extract routability information of local wire nets, resolving the adaptation issue between global routing and detailed routing. The proposed algorithm enhances routability information by an average of 16.07% across ten benchmark circuits. Additionally, a Generative Neural Network model based on Conditional Variational Autoencoder (CVAE) is employed to improve the efficiency of track assignment routing, yielding significant simulation results. Furthermore, a negotiation-based tear-and-reassign approach is utilized to address track congestion issues, resulting in an average optimization of 26.03% in overlap cost, with a tradeoff of sacrificing 6.67% of wirelength on average.

Background and Objectives: High-level synthesis (HLS) is one of the substantial steps in designing VLSI digital circuits. The primary purpose of HLS is to minimize the digital units used in the system to improve their power, delay, and area.Methods: In the modified MFO algorithm presented in this paper, a hyperbolic spiral is chosen as the update mechanism of moths. Also, by presenting a new approach, a paramount issue involved in applying meta-heuristic methods for solving HLS problems of VLSI circuits has been disentangled.Results: By comparing the performance of the proposed method with Genetic algorithm (GA)-based method and particle swarm optimization (PSO)-based method for the synthesis of the digital filters, it is concluded that the proposed method has the higher ability in the HLS of data path in digital filters. The best improvement is 2.78% for the delay (latency), 6.51% for the occupied area of the chip and 6.93% in power consumption. Another feature of the proposed method is its high-speed in finding optimal solutions, in a manner which, more than 21.6% and 12.9% faster than the GA-based and PSO-based methods, respectively on average.Conclusion: The most important very large scale integration (VLSI) circuits are digital filters and transformers, which are widely used in audio and video processing, medical signal processing, and telecommunication systems. The complex, expansive, and discrete nature of design space in high-level synthesis problems has made them one of the most difficult problems in VLSI circuit design.

For first time, we report a novel deep sub-micron fully-depleted silicon-on-insulator metal–oxide–semiconductor field-effect-transistor (FD SOI MOSFET) where the channel layer consists of two sections with a step doping (SD) region in order to increase performance and reliability of the device. This new structure that called SD FD SOI structure (SDFD-SOI MOSFET), were used for reaching suitable threshold voltage upon device scaling and reliability improvement. We demonstrate that the electric field was modified in the channel and common peak near the source junction have been reduced in the SDFD-SOI structure. The device demonstrates large enhancements in performance areas such as current drive capability, output resistance, hot-carrier reliability and threshold voltage roll-off. It was found that the device performance is very much dependent upon the SD region parameters. Simulation results show that the proposed structure improved on/off current ratio, and saturated output characteristics compared with conventional SOI structure (C-SOI MOSFET). Also, it was shown that substrate current of SDFD-SOI MOSFET is much lower than the C-SOI MOSFET which presented the lower hot-carrier degradation in proposed MOSFET. Results show that the most short-channel problems in very large scale integrated circuits (VLSI) could be solved and the proposed SDFD-SOI MOSFETs can work very well in deep sub-micron and nanoscale regime.

Systematic approaches to testing embedded analogue circuit functions

Graph partitioning applied to the logic testing of combinational circuits

Circuit design plays an essential role in all consumer electronics products. Printed circuit board (PCB) and very-largescale integration (VLSI) circuit designing requires optimization of the electronic components placement and wire routing to connect the components. Currently, circuit routing processes have been performed manually by experts, which greatly increases the cost of human resources and time. Such heuristic circuit designs are not optimized and may have errors, which is why automated circuit routing algorithms are important. However, it is difficult to obtain an optimal solution in circuit routing as it is an NPhard problem. In addition, poor circuit routing increases the wire length of the circuit, which causes an increase in circuit cost and weight as well as performance degradation. In order to achieve routing optimization, many technologies have been proposed, in which some have applied artificial intelligence (AI) to improve the overall performance and reduce the designing time. Accordingly, in this paper, routing problems in PCB and VLSI are explained, and proposed technologies to solve these routing problems are introduced. Especially, a detailed investigation and analysis of AI technologies grafted into circuit routing algorithms are explained, and the considerations for AI-based routing algorithms are presented.

A number of knowledge graph (KG)-based recommendation algorithms have been introduced; KGs enable users and items and their attributes to be treated in an integrated way and structural information to be captured through graphs. There are many variations of the KG based recommendation algorithms. Among them, KG embedding is often used, but doing this does not take advantage of the meta-path-level proximity between users and items. This paper presents a flexible framework combining random walk and KG embedding methods. The random walk model is formulated on the basis of the similarity between nodes revealed by the KG embedding. This enables the metapath level proximity of users and items to be efficiently utilized. Comparison testing demonstrated that the proposed framework performs better than random- walk-only methods and KG-embedding-only methods, and slightly better than the existing method we have extended.

Purpose – This paper aims to present a method for the efficient reduction of networks modelling parasitic couplings in very‐large‐scale integration (VLSI) circuits.