GRILAPE: Graph Representation Inductive Learning-based Average Power Estimation for Frontend ASIC RTL Designs

This paper introduces GLAAPE, a novel graph learning-assisted neural network model that enables fast, accurate, and transferable estimation of average power in gate-level combinational designs from Register Transfer Level (RTL) simulation. GLAAPE learns to propagate the average toggle rates by effectively embedding the structural information and logical function feature values as vectors on each logic cell of the netlist file. GLAAPE predicts the output toggle rates of combinational logic cells and hence the average power of the benchmark circuits from inputs obtained through RTL simulation without the requirement of gate-level simulation. We evaluate GLAAPE with the commercial gate-level power estimation tool for inference throughput, which is, on average, 15.69X faster. GLAAPE outperforms the commercial RTL Power estimation tool for average power estimation by achieving a mean improvement of 25.28%. We also compare GLAAPE with the state-of-the-art model GRANNITE to predict the output toggle rates to demonstrate the transferability and achieve better accuracy with a mean improvement of 13.95%. We consider a good range of benchmark circuits for analysis, and our experimental results show the generalization and efficacy capability of GLAAPE.

This paper describes a technique to handle temporal signal correlations during estimation of average power in sequential circuits. A key feature of the approach is that it provides an efficient and accurate way to estimate average power using a Monte Carlo based method. Results on a large number of benchmark sequential circuits confirm that the technique runs efficiently (up to two orders of magnitude better than long run simulation) and yields accurate estimation of average power (on an average within 1% of long run simulation result). Results also indicate that if temporal correlations are ignored, the estimates of average power can be off by more than 55% for some benchmark circuits.

In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the observation that most power estimation tools typically perform the following sequence of operations: simulating the circuit to obtain value traces or statistics for the inputs of its constituent components, evaluating power models for each circuit component based on the input values seen during simulation, and aggregating the power consumption of individual components to compute the circuit's power consumption. We further recognize that the steps involved in power estimation (power model evaluation, aggregation) can themselves be thought of as synthesizable functions and implemented as hardware circuits. Thus, any given design can be enhanced by adding to it .power estimation hardware., and the resulting power model enhanced circuit can be mapped onto a hardware prototyping platform. While drastic speedups in power estimation (orders of magnitude) are possible using this approach, a significant challenge arises due to the increase in circuit size as a result of adding power estimation hardware. We propose a systematic methodology to reduce the size of the power model enhanced circuit through a suite of techniques, including power model reuse across different circuit components, regulating the granularity of components for power modeling, exploiting inter-component power correlations, resource sharing for power model computations, and the use of block memories for efficient storage within power models. We demonstrate the benefits of the proposed power emulation paradigm by applying it to register-transfer level (RTL) power estimation for industrial designs, resulting in speedups from around 10X to over 500X compared to state-of-the-art commercial power estimation tools.

This paper presents a sample-based energy simulation methodology that enables fast and accurate estimations of performance and average power for arbitrary RTL designs. Our approach uses an FPGA to simultaneously simulate the performance of an RTL design and to collect samples containing exact RTL state snapshots. Each snapshot is then replayed in gate-level simulation, resulting in a workload-specific average power estimate with confidence intervals. For arbitrary RTL and workloads, our methodology guarantees a minimum of four-orders-of-magnitude speedup over commercial CAD gate-level simulation tools and gives average energy estimates guaranteed to be within 5% of the true average energy with 99% confidence. We believe our open-source sample-based energy simulation tool Strober can not only rapidly provide ground truth for more abstract power models, but can enable productive design-space exploration early in the RTL design process.

Virtual platform prototypes are widely utilized to enable early system-level design space exploration. Accurate power models for hardware components at high levels of abstraction are needed to enable system-level power analysis and optimization. However, the limited observability of third party IPs renders traditional power modeling methods challenging and inaccurate. In this paper, we present a novel approach for extending behavioral models of black-box hardware IPs with an accurate power estimate. We leverage state-of-the-art-machine learning techniques to synthesize an abstract power model. Our model uses input and output history to track data-dependent pipeline behavior. Furthermore, we introduce a specialized ensemble learning that is composed out of individually selected cycle-by-cycle models to reduce overall complexity and further increase estimation accuracy. Results of applying our approach to various industrial-strength design examples shows that our models predict average power consumption to within 3% of a commercial gate-level power estimation tool, all while running several orders of magnitude faster.

Power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. In this paper, we present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to uncertainties in specification of primary inputs. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using Monte Carlo-based approaches. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately.

Early stage power estimation is critical for SoC architecture exploration and validation in modern VLSI design, but real-time, long time interval and accurate estimation is still challenging for system-level estimation and software/hardware tuning. This work proposes a model abstraction approach for real-time power estimation in the manner of machine learning. The singular value decomposition (SVD) technique is exploited to abstract the principle components of relationship between register toggling profile and accurate power waveform. The abstracted power model is automatically instrumented to RTL implementation and synthesized into FPGA platform for real-time power estimation by instrumenting the register toggling profile. The prototype implementation on three IP cores predicts the cycle-by-cycle power dissipation within 5% accuracy loss compared with a commercial power estimation tool.

Abstract. In this paper, surface wind speed and average wind power derived from Sentinel-1 Synthetic Aperture Radar Level 2 Ocean (OCN) product were validated against four weather buoys and three coastal weather stations around Ireland. A total of 1544 match-up points was obtained over a 2-year period running from May 2017 to May 2019. The match-up comparison showed that the satellite data underestimated the wind speed compared to in situ devices, with an average bias of 0.4 m s−1, which decreased linearly as a function of average wind speed. Long-term statistics using all the available data, while assuming a Weibull law for the wind speed, were also produced and resulted in a significant reduction of the bias. Additionally, the average wind power was found to be consistent with in situ data, resulting in an error of 10 % and 5 % for weather buoys and coastal stations, respectively. These results show that the Sentinel-1 Level 2 OCN product can be used to estimate the wind resource distribution, even in coastal areas. Maps of the average and seasonal wind speed and wind power illustrated that the error was spatially dependent, which should be taken into consideration when working with Sentinel-1 Synthetic Aperture Radar data.

Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design optimization through a framework that exploits the abstraction aspect of high-level designs and the availability aspect of well-established tool flows for RTL designs. Thereby, utilizing the best from both worlds (high-level and low-level) to bring forth a fast and accurate enough solution to a well-known problem in the design of low power embedded systems and SoCs. In this paper, the focus is on how to apply our approach on a deign of reasonable complexity. We present the case study of a power state machine controller that is a critical component of most power-aware embedded systems. The approach uses verification collaterals such as test content, assertions, etc., which are normally built during the verification process of a high-level design to enable power profiling and estimation. The presented methodology is specific to a high-level synthesis and power estimation framework.

Power analysis is an important and efficient mean for side channel attacks on security applications. By monitoring devices' power consumption during various operations it is possible to collect security information (e.g. the encryption key). These power drop-offs counter effects could be reduced or even eliminated, if accurate power estimations could be achieved on the early design cycles. It is crucial for the designers, to be able to evaluate accurately the power consumption during the development process, especially for the widely used, power consuming, security algorithms. This paper presents and compares the estimated and measured power consumption of security algorithms on both Xilinx and Altera FPGAs. The estimation numbers are produced using each vendor's commercial power estimation tool.The differences between measured and estimated power consumption, varied from 15.52% to 208% for the Xilinx devices and from 5.64% to 32.15% for the Altera device.As a result, although Altera's PowerPlay power estimation tool gene/rated more accurate results than Xilinx's Xpower tool, none of them seems to be yet mature enough for the very demanding security era.

Data center demand is projected to increase dramatically over the coming decades, creating concerns about their carbon footprint and motivating the design of methods that can scale data center capabilities sustainably. One such method is Demand Response (DR), which provides incentives for power consumers to regulate their consumption in compliance with sustainability and capacity needs in the grid. One limitation of existing work in data center DR is the computational expense of generating accurate average power estimates and flexibility forecasts for a data center, given knowledge about the data center's configuration and activity. We introduce CONDOR, a machine learning (ML) method to learn the relationship between a data center's configuration (e.g., power, performance, and load characteristics) and an objective function incorporating DR savings, energy cost, and workload quality-of-service (QoS) compliance. CONDOR optimizes power and flexible reserve estimates that minimize an objective function, helping the data center efficiently meet compliance with sustainability measures. Our results demonstrate that CONDOR achieves speed increases of around 15,000x in computing accurate forecasts compared to simulation-based estimation, which enables DR participation of large real-world data centers in DR programs without debilitating computational overhead.

Optimizing power dissipation is now a major concern in IC design. Accurate power estimation at the circuit level is too expensive. Tools which estimate power dissipation at higher levels of abstraction without sacrificing accuracy are of interest. We discuss a new cell-library based technique for power estimation. An I/O transition model is developed to represent energy consumption in library elements. Power estimation based on the I/O model requires less computational effort than with previous models. The I/O model also addresses accuracy limitation of previous models. A power estimation tool IOTA, based on this model, has been implemented in C and Matlab. For reasonably large combinational and sequential arithmetic circuits, IOTA has an average error of 5% and low simulation time compared to SPICE simulations.

This paper presents an efficient and accurate Monte-Carlo approach to the problem of estimating average node switching probabilities in sequential circuits which are used in average power estimation and reliability analysis of these circuits. Specific error bounds for the proposed estimation method are given at a certain level of confidence. This method is based on the analysis of paths in the State Transition Graph (STG) of the circuit and is validated by both theoretical analysis as well as experimental results.

A new method is presented for estimating the mobile speed and the average received power in general wireless propagation environments. The locally stationary received signal is expanded in a local exponential basis using best basis methods of wavelet analysis. An estimate of the time-varying Doppler power spectrum is obtained together with an estimate of the maximum Doppler frequency, which is proportional to the mobile speed. The average received power is then estimated by integrating the time-varying spectrum. Simulations demonstrate good tracking of variable mobile speed and average received power for a wide range of angular distributions of incident power. The estimator is shown to perform significantly better than an adaptive averaging method described in the literature. The speed and average power estimates are also used to detect the corner effect in urban cellular systems to improve handoff performance and reduce the call dropping rate.

Various power estimation methods with high-level hardware power model, i.e. power emulation, had been proposed to overcome the slow speed of traditional power estimation in software environment. But precise speed comparison between gate-level simulation and high-level power emulation was conducted rarely. In this paper, we propose an architecture of power emulation which can compare precise speed gain against the traditional power simulation. Experimental results show that the average power error is 0.29%, the power emulation analyzes power 20,206 times faster than the traditional power simulation.