Power Emulation Using a Power Model Based on Multiple Linear Regression

In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the observation that most power estimation tools typically perform the following sequence of operations: simulating the circuit to obtain value traces or statistics for the inputs of its constituent components, evaluating power models for each circuit component based on the input values seen during simulation, and aggregating the power consumption of individual components to compute the circuit's power consumption. We further recognize that the steps involved in power estimation (power model evaluation, aggregation) can themselves be thought of as synthesizable functions and implemented as hardware circuits. Thus, any given design can be enhanced by adding to it .power estimation hardware., and the resulting power model enhanced circuit can be mapped onto a hardware prototyping platform. While drastic speedups in power estimation (orders of magnitude) are possible using this approach, a significant challenge arises due to the increase in circuit size as a result of adding power estimation hardware. We propose a systematic methodology to reduce the size of the power model enhanced circuit through a suite of techniques, including power model reuse across different circuit components, regulating the granularity of components for power modeling, exploiting inter-component power correlations, resource sharing for power model computations, and the use of block memories for efficient storage within power models. We demonstrate the benefits of the proposed power emulation paradigm by applying it to register-transfer level (RTL) power estimation for industrial designs, resulting in speedups from around 10X to over 500X compared to state-of-the-art commercial power estimation tools.

Early stage power estimation is essential for hardware optimization but is challenging. In this paper, we propose GRILAPE, a graph representation inductive learning based average power estimation model using a novel graph attention-based mechanism that enables accurate, fast and transferable estimation of the average power of frontend ASIC RTL designs from RTL simulation without doing gate-level simulation. GRILAPE learns to propagate the toggle rates by replicating the logic computation procedure by embedding the feature values as vectors on each logic cell of the netlist file and estimating average power. We have achieved a mean improvement of 23.4% in average power estimation than the commercial RTL power estimation tool and 15.46X faster than the commercial gatelevel power estimation tool. We evaluate GRILAPE with state-of-the-art model GRANNITE to predict the output toggle rates for transferability and achieve better accuracy with a mean improvement of 14.36%. Our experimental results show the generalization and efficacy capability of GRILAPE.

This paper presents a sample-based energy simulation methodology that enables fast and accurate estimations of performance and average power for arbitrary RTL designs. Our approach uses an FPGA to simultaneously simulate the performance of an RTL design and to collect samples containing exact RTL state snapshots. Each snapshot is then replayed in gate-level simulation, resulting in a workload-specific average power estimate with confidence intervals. For arbitrary RTL and workloads, our methodology guarantees a minimum of four-orders-of-magnitude speedup over commercial CAD gate-level simulation tools and gives average energy estimates guaranteed to be within 5% of the true average energy with 99% confidence. We believe our open-source sample-based energy simulation tool Strober can not only rapidly provide ground truth for more abstract power models, but can enable productive design-space exploration early in the RTL design process.

The subsystem in a smartphone means its hardware components, such as the CPU, GPU, and screen. Accurately estimating subsystem power consumption of commercial smartphones is necessary for applicable to wide research areas. Current subsystem power estimation techniques are mostly based on power models, resulting in considerable errors for various types of power consumption behaviors. These include (1) asynchrony between the measured power consumption and the corresponding workload statistics, and (2) nonlinearity concerning CPU idle states, pixels colors of AMOLED screen, and GPU workload statistics. In this study, we propose a novel utilization-based, subsystem power estimation method for a smartphone, namely Clustering and Symbolic Regression (CSR) that takes these power consumption behaviors into account so as to increase power estimation accuracy. To address asynchrony, we cluster the subsystem workload statistics into synchronous and asynchronous groups by employing affinity propagation clustering. To address nonlinearity, we employ symbolic regression for fitting measured power consumptions with respect to subsystem workload statistics. We compare our approach with various power estimation methods, Linear Regression Model (LM), Genetic Programming (GP), and Support Vector Regression (SVR). The results show Mean Absolute Percentage Error (MAPE) reduction between 23.61 and 42.55 percent on the estimated power consumption of a simple (Nexus S) and complex (Galaxy S4) smartphone subsystems.

Today's smartphone application (hereinafter 'app') markets miss a key piece of information, power consumption of apps. This causes a severe problem for continuous sensing apps as they consume significant power without users' awareness. Users have no choice but to repeatedly install one app after another and experience their power use. To break such an exhaustive cycle, we propose PowerForecaster, a system that provides users with power use of sensing apps at pre-installation time. Such advanced power estimation is extremely challenging since the power cost of a sensing app largely varies with users' physical activities and phone use patterns. We observe that the time for active sensing and processing of an app can vary up to three times with 27 people's sensor traces collected over three weeks. PowerForecaster adopts a novel power emulator that emulates the power use of a sensing app while reproducing users' physical activities and phone use patterns, achieving accurate, personalized power estimation. Our experiments with three commercial apps and two research prototypes show that PowerForecaster achieves 93.4% accuracy under 20 use cases. Also, we optimize the system to accelerate emulation speed and reduce overheads, and show the effectiveness of such optimization techniques.

Using the data obtained from a battery monitoring unit (BMU) are a low-cost, easy-to-use way to estimate the power consumption of smartphones. Current online power estimation methods produce significant errors compared to using external power monitors because online methods do not address the three most important factors which affect the efficacy of online power consumption estimates. These are: (1) battery capacity degradation with aging, (2) asynchronous power consumption, and (3) the effect of state-of-charge (SoC) difference, the remaining power level of the battery. This paper presents a semi-online power estimate method which uses charging data to determine actual battery capacity, applies the discrepancy between battery voltage at different workloads for asynchronous power detection, and analyzes the range of SoC (0-100 percent) which causes minimal power estimate errors. The proposed method is validated by conducting a series of experiments on a smartphone and comparing the results with the existing online power estimation methods. Experimental results on the power consumption estimates of real applications indicate that the semi-online method reduced the error rate of power estimates obtained from existing online methods by 27-94 percent. Moreover, this work also shows that battery capacity degradation is the major factor affecting the efficacy of online power estimations.

In this paper one method of optimizing a digital finite impulse response (FIR) filter has been illustrated. The advantages and disadvantages of several architectures and of the circuit modeling were presented using a standard toggle-based method for the circuit power estimation, gate-level simulations and synthesis. We showed that we can achieve a significant power reduction from the beginning by carefully selecting the right architecture and optimizing the VHDL code description of the module. The analysis was made based on the unity delay model and not on the physical extracted layout for a 150nm technology but the method can be used for other technologies as well.

Power calculations of a statistical test require that the underlying population distribution(s) be completely specified. Statisticians, in practice, may not have complete knowledge of the entire nature of the underlying distribution(s) and are at a loss for calculating the exact power of the test. In such cases, an estimate of the power would provide a suitable substitute. In this paper, we are interested in estimating the power of the Kruskal‐Wallis one‐way analysis of variance by ranks test for a location shift.We investigated an extension of a data‐based power estimation method presented by Collings and Hamilton (1988), which requires no prior knowledge of the underlying population distributions other than necessary to perform the Kruskal‐Wallis test for a location shift. This method utilizes bootstrapping techniques to produce a power estimate based on the empirical cumulative distribution functions of the sample data. We performed a simulation study of the extended power estimator under the conditions ofk= 3 andk= 5 samples of equal sizesm= 10 andm= 20, with four underlying continuous distributions that possessed various location configurations. Our simulation study demonstates that the Extended Average × & Y power estimation method is a reliable estimator of the power of the Kruskal‐Wallis test fork= 3 samples, and a more conservative to a mild overestimator of the true power fork= 5 samples.

This paper presents a novel high-level analytical approach to estimate logic power consumption of multipliers implemented in FPGAs in the presence of glitching and correlation. The proposed methodology is based on: 1) an analytical model for the switching activity of the component, and 2) a structural analysis of the FPGA implementation of the component. The complete model is parameterized in terms of complexity factors such as word-lengths and signal statistics of the operands. It also accounts for the glitching introduced by the component. Compared to the other power estimation methods, the number of circuit simulations needed for characterizing the power model of the component is highly reduced. The accuracy of the model is within 10% of low-level power estimates given by the tool XPower and it achieves better performance than other proposed high-level approaches.

A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified up-front by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 ip-ops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flip-flops).

This paper describes a technique to handle temporal signal correlations during estimation of average power in sequential circuits. A key feature of the approach is that it provides an efficient and accurate way to estimate average power using a Monte Carlo based method. Results on a large number of benchmark sequential circuits confirm that the technique runs efficiently (up to two orders of magnitude better than long run simulation) and yields accurate estimation of average power (on an average within 1% of long run simulation result). Results also indicate that if temporal correlations are ignored, the estimates of average power can be off by more than 55% for some benchmark circuits.

With the advance of VLSI technology, power consumption of chips has become a major concern in the state of art CMOS circuits design. Among all kinds of previous power analysis methods, the gate-level power analysis can give a relatively accurate result and has been commonly used. However, the simulation speed is very low due to large amount switching activity records for all gate-level cells. In this paper, we proposed a novel method to accelerate gate-level power simulation and estimation. The experimental results based on actual gate-level netlist of Godson-2 processor[1] have shown that the proposed method can improve simulation speed by about 20 times compared with traditional gate-level power calculation, and the error of power analysis result is less than 5%.

A detailed analysis of power consumption at low-system levels becomes important as a means for reducing the overall power consumption of a system and in order to gain performance by avoiding thermal hotspots that reduce system’s frequency. This work presents a new power estimation method that allows understanding the contribution of different architectural components on the power breakdown of an application. To demonstrate the usefulness of the new proposed tool and methodology, we choose to examine this new methodology while using modern processor architecture such as the newly released Intel Skylake processor while executing the entire SPEC CPU2006 benchmark suite. This chapter will provide a detailed power and performance characterization report for the SPEC CPU2006 benchmarks, analysis of the data using side-by-side power, and performance breakdowns, as well as few other interesting case studies.

This paper introduces GLAAPE, a novel graph learning-assisted neural network model that enables fast, accurate, and transferable estimation of average power in gate-level combinational designs from Register Transfer Level (RTL) simulation. GLAAPE learns to propagate the average toggle rates by effectively embedding the structural information and logical function feature values as vectors on each logic cell of the netlist file. GLAAPE predicts the output toggle rates of combinational logic cells and hence the average power of the benchmark circuits from inputs obtained through RTL simulation without the requirement of gate-level simulation. We evaluate GLAAPE with the commercial gate-level power estimation tool for inference throughput, which is, on average, 15.69X faster. GLAAPE outperforms the commercial RTL Power estimation tool for average power estimation by achieving a mean improvement of 25.28%. We also compare GLAAPE with the state-of-the-art model GRANNITE to predict the output toggle rates to demonstrate the transferability and achieve better accuracy with a mean improvement of 13.95%. We consider a good range of benchmark circuits for analysis, and our experimental results show the generalization and efficacy capability of GLAAPE.

This paper presents a methodology to generate a hierarchy of power models for power estimation of custom hardware IP blocks, enabling a trade-off between power estimation accuracy, modeling effort and estimation speed. Our power estimation approach enables several novel system-level explorations - such as observing the effect of clock gating, and the effects of tweaking application-level parameters on system power - with an estimation accuracy that is close to the gate-level. We implemented our methodology on an H.264 video decoder prediction IP case study, created power models, and evaluated the effects of varying design parameters (e.g., clock gating, IIP frame ratios, quantization), allowing rapid system-level power exploration of these design parameters.