System level power estimation methodology with H.264 decoder prediction IP case study

Virtual platform prototypes are widely utilized to enable early system-level design space exploration. Accurate power models for hardware components at high levels of abstraction are needed to enable system-level power analysis and optimization. However, the limited observability of third party IPs renders traditional power modeling methods challenging and inaccurate. In this paper, we present a novel approach for extending behavioral models of black-box hardware IPs with an accurate power estimate. We leverage state-of-the-art-machine learning techniques to synthesize an abstract power model. Our model uses input and output history to track data-dependent pipeline behavior. Furthermore, we introduce a specialized ensemble learning that is composed out of individually selected cycle-by-cycle models to reduce overall complexity and further increase estimation accuracy. Results of applying our approach to various industrial-strength design examples shows that our models predict average power consumption to within 3% of a commercial gate-level power estimation tool, all while running several orders of magnitude faster.

In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the observation that most power estimation tools typically perform the following sequence of operations: simulating the circuit to obtain value traces or statistics for the inputs of its constituent components, evaluating power models for each circuit component based on the input values seen during simulation, and aggregating the power consumption of individual components to compute the circuit's power consumption. We further recognize that the steps involved in power estimation (power model evaluation, aggregation) can themselves be thought of as synthesizable functions and implemented as hardware circuits. Thus, any given design can be enhanced by adding to it .power estimation hardware., and the resulting power model enhanced circuit can be mapped onto a hardware prototyping platform. While drastic speedups in power estimation (orders of magnitude) are possible using this approach, a significant challenge arises due to the increase in circuit size as a result of adding power estimation hardware. We propose a systematic methodology to reduce the size of the power model enhanced circuit through a suite of techniques, including power model reuse across different circuit components, regulating the granularity of components for power modeling, exploiting inter-component power correlations, resource sharing for power model computations, and the use of block memories for efficient storage within power models. We demonstrate the benefits of the proposed power emulation paradigm by applying it to register-transfer level (RTL) power estimation for industrial designs, resulting in speedups from around 10X to over 500X compared to state-of-the-art commercial power estimation tools.

Fast and accurate power estimation has become an important topic with the increasing need for low power electronics. In this paper we address the problem of using event-driven simulation tools for power estimation. We identify and compare two approaches: input-driven and output-driven, and propose several ways of improvement. The estimation accuracy is degraded in event-driven power estimators due to superfluous and partial glitches. We described glitch filtering and estimation techniques pertaining to input-driven and output-driven power estimators. An output-driven power estimator, Peony, was developed which used the proposed path power idea to improve the estimation accuracy. It achieved significant power estimation accuracy improvement at a speed of two orders of magnitude faster than Spice.

Embedded memories have been used extensively in modern SoC designs. In order to estimate the power consumption of an entire design correctly, an accurate memory power models are needed. However, the memory power model that is commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effects with scaling capability. The proposed approach is very useful to be combined with the memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into the existing power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.

Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation. In this paper, some respective low power design techniques at RTL are re-investigated at tsmc 45 nanometer CMOS technology. Clock gating (CG) is one of the most widely used and effective technique in RTL low power design. Without the enable signal, bus-specific clock gating (BSC) and threshold-based clock gating (TCG) are considered. Also an improved active-driven optimized bus-specific clock gating (OBSC) is proposed in our laboratory. When the enable signal is taken into account, this paper explains local-explicit clock gating (LECG), enhanced clock gating (ECG), waste-toggle-rate-based (WTR) clock gating and the single comparator-based clock gating (SCCG) techniques. Operand isolation is another useful design technique for reducing the power consumption by blocking some redundant operations. Memory splitting is an effective design solution for low power design as well. These techniques have been experimented by using tsmc 45nm technology library and the proposed low-power RTL techniques are evaluated at gate level with logic synthesis results.

Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design optimization through a framework that exploits the abstraction aspect of high-level designs and the availability aspect of well-established tool flows for RTL designs. Thereby, utilizing the best from both worlds (high-level and low-level) to bring forth a fast and accurate enough solution to a well-known problem in the design of low power embedded systems and SoCs. In this paper, the focus is on how to apply our approach on a deign of reasonable complexity. We present the case study of a power state machine controller that is a critical component of most power-aware embedded systems. The approach uses verification collaterals such as test content, assertions, etc., which are normally built during the verification process of a high-level design to enable power profiling and estimation. The presented methodology is specific to a high-level synthesis and power estimation framework.

In this paper we present an effective technique for compacting a large sequence of input vectors into a much shorter one so as to reduce the circuit-level simulation time by orders of magnitude and maintain the accuracy of the power estimates. In particular, we model the effects of complex spatiotemporal correlations and rise/fall time slopes on total power dissipation. As the results demonstrate, large compaction ratios of orders of magnitude can be obtained without significant loss (about 5%, on average) in the accuracy of power estimates.

FPGA is a promising hardware accelerator in modern high-performance computing systems, e.g. cloud computing, big-data processing, etc. In such a system, power is a key factor of the design requiring thermal and energy-saving considerations. Modern power estimators for FPGA either support specific hardware provided by vendors or contain power models for certain types of conventional FPGA architectures. However, with technology advancement, novel FPGA of versatile architectures are introduced to further augment current FPGA architecture at various aspects, such as emerging FPGA with non-volatile memory, nanowire interconnection of reconfigurable array, etc. To evaluate the power consumption of various FPGA designs, the power estimator has to be made more flexible and extendable for supporting new devices and architectures. We introduce in this paper a novel power estimator with hierarchical library supporting power models at different levels, e.g. novel circuit of components, emerging memory devices, architecture of timemultiplexing fashion, etc. The power estimator also supports coarse-grain or fine-grain power estimation defined by users for achieving complexity-accuracy trade-off. Simulation results of benchmarks of our power estimator against commercial one demonstrate accuracy of our tool. Furthermore, we present an example of RRAM FPGA power estimation, which has novel memory devices and potential of power gating. Our tool demonstrates flexibility to well support, but not limited to, the power estimation of such state-of-the-art FPGAs.

We propose a new power simulation technique that effectively considers dynamic program execution behaviors such as cache hit/miss or branch predicted/mis-predicted and achieves fast and accurate power estimation results. Traditionally, accurate software power estimation relies on slower fine-grained simulations while faster coarse-grained simulations often lead to inaccurate estimation results. We pre-characterize detailed circuit power consumption, pipeline and branch effects of each basic block for accuracy and then apply efficient instruction-set simulators to compute total software power consumption. The experimental result shows that our approach achieves over 200 MIPS performance with a less than 3% error rate.

Early stage power estimation is critical for SoC architecture exploration and validation in modern VLSI design, but real-time, long time interval and accurate estimation is still challenging for system-level estimation and software/hardware tuning. This work proposes a model abstraction approach for real-time power estimation in the manner of machine learning. The singular value decomposition (SVD) technique is exploited to abstract the principle components of relationship between register toggling profile and accurate power waveform. The abstracted power model is automatically instrumented to RTL implementation and synthesized into FPGA platform for real-time power estimation by instrumenting the register toggling profile. The prototype implementation on three IP cores predicts the cycle-by-cycle power dissipation within 5% accuracy loss compared with a commercial power estimation tool.

The subsystem in a smartphone means its hardware components, such as the CPU, GPU, and screen. Accurately estimating subsystem power consumption of commercial smartphones is necessary for applicable to wide research areas. Current subsystem power estimation techniques are mostly based on power models, resulting in considerable errors for various types of power consumption behaviors. These include (1) asynchrony between the measured power consumption and the corresponding workload statistics, and (2) nonlinearity concerning CPU idle states, pixels colors of AMOLED screen, and GPU workload statistics. In this study, we propose a novel utilization-based, subsystem power estimation method for a smartphone, namely Clustering and Symbolic Regression (CSR) that takes these power consumption behaviors into account so as to increase power estimation accuracy. To address asynchrony, we cluster the subsystem workload statistics into synchronous and asynchronous groups by employing affinity propagation clustering. To address nonlinearity, we employ symbolic regression for fitting measured power consumptions with respect to subsystem workload statistics. We compare our approach with various power estimation methods, Linear Regression Model (LM), Genetic Programming (GP), and Support Vector Regression (SVR). The results show Mean Absolute Percentage Error (MAPE) reduction between 23.61 and 42.55 percent on the estimated power consumption of a simple (Nexus S) and complex (Galaxy S4) smartphone subsystems.

In this work, we propose an electronic system-level (ESL) power estimation framework which can support several low power methodologies such as dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM). Based on the proposed framework, designers can analyze the system power and develop the suitable low power strategies for different applications in the early design stage. The proposed framework had been applied to a heterogeneous multi-core platform. We rapidly characterized the required power models by using physical power measurement to construct the ESL power estimation environment. According to the experimental results, using the proposed framework can have quite accurate power estimation and correct power trend prediction in different voltage/frequency conditions. We also had demonstrated that the low power methodologies can be analyzed and simulated based on this framework.

The advancement in wireless telecommunication technologies like 3G, 4G and now 5G enrich the demand of high performance portable devices, operating at high frequencies i.e. from few hundred MHz to several GHz. High performance can only be achieved at the cost of high power dissipation. Nowadays, the use of FPGAs is rapidly increasing due to its low cost and smaller time to market. Today’s high end FPGAs are capable of implementing high performance designs such as transceivers for RF application, signal processing and image processing applications etc. This is only possible due to their complex designs that includes on chip dedicated multipliers, Dual RAM blocks, Ethernet and DCMs etc. Since FPGAs consume large amount of power, it becomes a challenge for the designers to implement low power battery operated communication systems. Several power estimation models are available in literature for early stage power estimation of FPGAs in the synthesis design flow but they provide less accuracy (high percentage error) for the designs incorporated with low power reduction technique. This paper presents the limitation of existing power estimation model proposed by Deng. The given model is converted into a script using MATLAB. The power values estimated from the power model (script) are compared with the high level synthesis tool: Xpower Analyzer targeted to Virtex FPGA. For estimation of power values, an embedded multiplier is synthesized for two different configurations: one with ‘CE’ (low power) and another without ‘CE’ for different I/O vector length. The results suggested that the given low level power estimation models provide less accuracy (high % error) for the designs incorporated with low power reduction technique i.e. with ‘CE’. Further, there is a scope of remodel the existing model for the observed shortcoming.

Early stage power estimation is essential for hardware optimization but is challenging. In this paper, we propose GRILAPE, a graph representation inductive learning based average power estimation model using a novel graph attention-based mechanism that enables accurate, fast and transferable estimation of the average power of frontend ASIC RTL designs from RTL simulation without doing gate-level simulation. GRILAPE learns to propagate the toggle rates by replicating the logic computation procedure by embedding the feature values as vectors on each logic cell of the netlist file and estimating average power. We have achieved a mean improvement of 23.4% in average power estimation than the commercial RTL power estimation tool and 15.46X faster than the commercial gatelevel power estimation tool. We evaluate GRILAPE with state-of-the-art model GRANNITE to predict the output toggle rates for transferability and achieve better accuracy with a mean improvement of 14.36%. Our experimental results show the generalization and efficacy capability of GRILAPE.

Optimizing power dissipation is now a major concern in IC design. Accurate power estimation at the circuit level is too expensive. Tools which estimate power dissipation at higher levels of abstraction without sacrificing accuracy are of interest. We discuss a new cell-library based technique for power estimation. An I/O transition model is developed to represent energy consumption in library elements. Power estimation based on the I/O model requires less computational effort than with previous models. The I/O model also addresses accuracy limitation of previous models. A power estimation tool IOTA, based on this model, has been implemented in C and Matlab. For reasonably large combinational and sequential arithmetic circuits, IOTA has an average error of 5% and low simulation time compared to SPICE simulations.