A basic-block power annotation approach for fast and accurate embedded software power estimation

Fast and accurate power estimation has become an important topic with the increasing need for low power electronics. In this paper we address the problem of using event-driven simulation tools for power estimation. We identify and compare two approaches: input-driven and output-driven, and propose several ways of improvement. The estimation accuracy is degraded in event-driven power estimators due to superfluous and partial glitches. We described glitch filtering and estimation techniques pertaining to input-driven and output-driven power estimators. An output-driven power estimator, Peony, was developed which used the proposed path power idea to improve the estimation accuracy. It achieved significant power estimation accuracy improvement at a speed of two orders of magnitude faster than Spice.

Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design optimization through a framework that exploits the abstraction aspect of high-level designs and the availability aspect of well-established tool flows for RTL designs. Thereby, utilizing the best from both worlds (high-level and low-level) to bring forth a fast and accurate enough solution to a well-known problem in the design of low power embedded systems and SoCs. In this paper, the focus is on how to apply our approach on a deign of reasonable complexity. We present the case study of a power state machine controller that is a critical component of most power-aware embedded systems. The approach uses verification collaterals such as test content, assertions, etc., which are normally built during the verification process of a high-level design to enable power profiling and estimation. The presented methodology is specific to a high-level synthesis and power estimation framework.

CAPE: A cross-layer framework for accurate microprocessor power estimation

Fine-grained power estimation is fundamental to modern MPSoC design and operation, enabling early power and thermal budgeting before fabrication, predictive thermal control at runtime, post-silicon microarchitectural energy debugging, and hardware security analysis. Existing System-on-Chip (SoC) designs often rely solely on total power consumption measurements because of the cost, size, and complexity of power sensors. However, the lack of precision and granularity in power measurements leads to inefficient power and thermal management and limits the ability to detect failed or compromised sensors. To tackle these challenges, we propose the Improved Clustering Blind Power Identification (ICBPI) approach, an innovative approach for fine-grained power estimation in SoCs. ICBPI leverages total power measurements and per-unit temperature data, even with potentially unreliable sensors, to deliver accurate per-unit power estimates. This dual focus not only enhances power estimation, leading to better power management decisions, but also improves the detection of malicious sensors—such as those compromised by hardware Trojan attacks—that manipulate sensor data to induce potential system failures. Extensive evaluations across four SoC architectures demonstrate ICBPI’s superior performance in reducing per-core power estimation errors by \({77.56\%} \) compared to the baseline Blind Power Identification (BPI) and by \({68.44\%} \) compared to the state-of-the-art approaches. Furthermore, ICBPI achieves \({100\%} \) detection of malicious thermal sensor attacks and enhances the localization process compared to the Blind Identification Countermeasure (BIC) approach. In the comparative analysis between ICBPI and the most recent model, Alternating Blind Power Identification (ABPI), ICBPI shows error rates as low as \({0.5\%} \) compared to \({2.8\%} \) in a 2 × 2 mesh benchmark and outperforms ABPI on heterogeneous architectures. The NVIDIA Jetson Xavier AGX development board serves as a platform for validating ICBPI. Consequently, ICBPI demonstrates an approximate reduction in average error of \(79.71\% \) on the CPU and \(79.59\% \) on the GPU relative to three existing state-of-the-art approaches.

Power analysis is an important and efficient mean for side channel attacks on security applications. By monitoring devices' power consumption during various operations it is possible to collect security information (e.g. the encryption key). These power drop-offs counter effects could be reduced or even eliminated, if accurate power estimations could be achieved on the early design cycles. It is crucial for the designers, to be able to evaluate accurately the power consumption during the development process, especially for the widely used, power consuming, security algorithms. This paper presents and compares the estimated and measured power consumption of security algorithms on both Xilinx and Altera FPGAs. The estimation numbers are produced using each vendor's commercial power estimation tool.The differences between measured and estimated power consumption, varied from 15.52% to 208% for the Xilinx devices and from 5.64% to 32.15% for the Altera device.As a result, although Altera's PowerPlay power estimation tool gene/rated more accurate results than Xilinx's Xpower tool, none of them seems to be yet mature enough for the very demanding security era.

Temperature estimation and prediction are critical for online regulation of temperature and hot spots on today's high performance processors. In this paper, we present a new method, called FRETEP, to accurately estimate and predict the full-chip temperature at runtime under more practical conditions where we have inaccurate thermal model, less accurate power estimations and limited number of on-chip physical thermal sensors. FRETEP employs a number of new techniques to address this problem. First, we propose a new thermal sensor based error compensation method to correct the errors due to the inaccuracies in thermal model and power estimations. Second, we raise a new correlation based method for error compensation estimation with limited number of thermal sensors. Third, we optimize the compact modeling technique and integrate it into the error compensation process in order to perform the thermal estimation with error compensation at runtime. Last but not least, to enable accurate temperature prediction for the emerging predictive thermal management, we design a full-chip thermal prediction framework employing time series prediction method. Experimental results show FRETEP accurately estimates and predicts the full-chip thermal behavior with very low overhead introduced and compares very favorably with the Kalman filter based approach on standard SPEC benchmarks.

This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days.

Virtual platform prototypes are widely utilized to enable early system-level design space exploration. Accurate power models for hardware components at high levels of abstraction are needed to enable system-level power analysis and optimization. However, the limited observability of third party IPs renders traditional power modeling methods challenging and inaccurate. In this paper, we present a novel approach for extending behavioral models of black-box hardware IPs with an accurate power estimate. We leverage state-of-the-art-machine learning techniques to synthesize an abstract power model. Our model uses input and output history to track data-dependent pipeline behavior. Furthermore, we introduce a specialized ensemble learning that is composed out of individually selected cycle-by-cycle models to reduce overall complexity and further increase estimation accuracy. Results of applying our approach to various industrial-strength design examples shows that our models predict average power consumption to within 3% of a commercial gate-level power estimation tool, all while running several orders of magnitude faster.

With the development of high-throughput sequencing and genotyping technologies, the number of markers collected in genetic association studies is growing rapidly, increasing the importance of methods for correcting for multiple hypothesis testing. The permutation test is widely considered the gold standard for accurate multiple testing correction, but it is often computationally impractical for these large datasets. Recently, several studies proposed efficient alternative approaches to the permutation test based on the multivariate normal distribution (MVN). However, they cannot accurately correct for multiple testing in genome-wide association studies for two reasons. First, these methods require partitioning of the genome into many disjoint blocks and ignore all correlations between markers from different blocks. Second, the true null distribution of the test statistic often fails to follow the asymptotic distribution at the tails of the distribution. We propose an accurate and efficient method for multiple testing correction in genome-wide association studies—SLIDE. Our method accounts for all correlation within a sliding window and corrects for the departure of the true null distribution of the statistic from the asymptotic distribution. In simulations using the Wellcome Trust Case Control Consortium data, the error rate of SLIDE's corrected p-values is more than 20 times smaller than the error rate of the previous MVN-based methods' corrected p-values, while SLIDE is orders of magnitude faster than the permutation test and other competing methods. We also extend the MVN framework to the problem of estimating the statistical power of an association study with correlated markers and propose an efficient and accurate power estimation method SLIP. SLIP and SLIDE are available at http://slide.cs.ucla.edu.

Optimizing power dissipation is now a major concern in IC design. Accurate power estimation at the circuit level is too expensive. Tools which estimate power dissipation at higher levels of abstraction without sacrificing accuracy are of interest. We discuss a new cell-library based technique for power estimation. An I/O transition model is developed to represent energy consumption in library elements. Power estimation based on the I/O model requires less computational effort than with previous models. The I/O model also addresses accuracy limitation of previous models. A power estimation tool IOTA, based on this model, has been implemented in C and Matlab. For reasonably large combinational and sequential arithmetic circuits, IOTA has an average error of 5% and low simulation time compared to SPICE simulations.

Early stage power estimation is essential for hardware optimization but is challenging. In this paper, we propose GRILAPE, a graph representation inductive learning based average power estimation model using a novel graph attention-based mechanism that enables accurate, fast and transferable estimation of the average power of frontend ASIC RTL designs from RTL simulation without doing gate-level simulation. GRILAPE learns to propagate the toggle rates by replicating the logic computation procedure by embedding the feature values as vectors on each logic cell of the netlist file and estimating average power. We have achieved a mean improvement of 23.4% in average power estimation than the commercial RTL power estimation tool and 15.46X faster than the commercial gatelevel power estimation tool. We evaluate GRILAPE with state-of-the-art model GRANNITE to predict the output toggle rates for transferability and achieve better accuracy with a mean improvement of 14.36%. Our experimental results show the generalization and efficacy capability of GRILAPE.

In this paper we summarize the techniques employed in tagged probabilistic simulation (TPS) to perform gate level power estimation. A prominent feature of TPS is the use of tagged probability waveforms to provide a more compact, yet detailed, waveform representation. This helps resolve several important shortcomings of conventional probabilistic simulation techniques in which the logical waveforms of each node are represented by a single probability waveform. Experimental results show that TPS can provide accuracy levels of 10-15% compared to circuit simulation in dynamic power estimation with run times orders of magnitude faster.

This paper presents a methodology for calculating very accurate mean power estimates for integrated digital CMOS circuits at gate level. It is shown that by means of improving the time and history handling algorithm of an event driven simulation system can increase the accuracy of predicted power consumption up to 20% compared to a previous, highly efficient method. The outlined approach is capable of handling complex circuits as well as very large sets of input vectors in an efficient way. It is demonstrated that the use of the proposed method, i.e. a specialized event oriented simulation system calibrated with gate specific parameters, results in overall estimation figures which are comparable to transistor level (SPICE) simulation accuracy and in a speed-up of about 10000. This allows both the simulation of very large circuits and the improvement of key design parameters such as yield during manufacturing process optimization, which typically requires repeated estimation runs. Experimental results for a benchmark circuit are detailed which demonstrate significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation methods.

In this work, we propose an electronic system-level (ESL) power estimation framework which can support several low power methodologies such as dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM). Based on the proposed framework, designers can analyze the system power and develop the suitable low power strategies for different applications in the early design stage. The proposed framework had been applied to a heterogeneous multi-core platform. We rapidly characterized the required power models by using physical power measurement to construct the ESL power estimation environment. According to the experimental results, using the proposed framework can have quite accurate power estimation and correct power trend prediction in different voltage/frequency conditions. We also had demonstrated that the low power methodologies can be analyzed and simulated based on this framework.

In mobile communications, accurate power estimation is important for power control and handoff decisions. Power estimation algorithms aim to filter out the fast variation in the received power due to multipath fading, and should ideally exhibit very low complexity. For this reason, linear filtering (local mean) is almost exclusively used for power estimation in practice. We derive the maximum likelihood estimator in an idealized setting, and motivated by the statistical properties of the multipath signal, we also propose median filtering for power estimation. Simulations show promising results, indicating gains in RMSE and robustness to increased window size.