Hardware Implementation of Depthwise Separable Convolution Neural Network

<p><span>Every year a number of rice diseases cause major damage to crop around the world. Early and accurate prediction of various rice plant diseases has been a major challenge for farmers and researchers. Recent developments in the convolutional neural networks (CNNs) have made image processing techniques more convenient and precise. Motivated from that in this research, a depthwise separable convolutional neural network based classification model has been proposed for identifying 12 types of rice plant diseases. Also, 8 different state-of-the-art convolution neural network model has been fine-tuned specifically for identifying the rice plant diseases and their performance has been evaluated. The proposed model performs considerably well in contrast to existing state-of-the-art CNN architectures. The experimental analysis indicates that the proposed model can correctly diagnose rice plant diseases with a validation and testing accuracy of 96.5% and 95.3% respectively while having a substantially smaller model size.</span></p>

Convolutional neural networks (CNNs) have been widely deployed in computer vision tasks. However, the computation and resource intensive characteristics of CNN bring obstacles to its application on embedded systems. This article proposes an efficient inference accelerator on Field Programmable Gate Array (FPGA) for CNNs with depthwise separable convolutions. To improve the accelerator efficiency, we make four contributions: (1) an efficient convolution engine with multiple strategies for exploiting parallelism and a configurable adder tree are designed to support three types of convolution operations; (2) a dedicated architecture combined with input buffers is designed for the bottleneck network structure to reduce data transmission time; (3) a hardware padding scheme to eliminate invalid padding operations is proposed; and (4) a hardware-assisted pruning method is developed to support online tradeoff between model accuracy and power consumption. Experimental results show that for MobileNetV2 the accelerator achieves 10× and 6× energy efficiency improvement over the CPU and GPU implementation, and 302.3 frames per second and 181.8 GOPS performance that is the best among several existing single-engine accelerators on FPGAs. The proposed hardware-assisted pruning method can effectively reduce 59.7% power consumption at the accuracy loss within 5%.

This study examines the effectiveness of deep learning techniques through a comparison of two of the widely used Convolutional Neural Network (CNN) architectures, SqueezeNet and MobileNet, on the CIFAR-10 and MNIST datasets in poor conditions. Both architectures were compared after numerous techniques had been used to enhance their accuracy. Based on the MNIST dataset, MobileNet achieved a training accuracy of 98.34% in conjunction with a validation accuracy of 91.40%, thus demonstrating its capability to tackle complex image recognition tasks. SqueezeNet, on the other hand, was poor with a training accuracy of 9.85% and a validation accuracy of 9.95%. When the CIFAR-10 dataset was employed, MobileNet achieved a training accuracy of 39.43% and a validation accuracy of 9.95%, while SqueezeNet achieved a training accuracy of 10.10% and a validation accuracy of 9.70%. This study indicates the significance of accuracyenhancing techniques and highlights the performance of different CNN architectures in poor conditions.

This paper demonstrates image classification using deep learning. Deep learning has the inherent ability to automatically discover and extract meaningful features for specific applications. Among the popular techniques in deep learning, the convolutional neural network (CNN) stands out. CNN consists of an input layer, hidden layers, and an output layer, where meaningful features are automatically extracted from input images. This paper presents the performance and identifies the most effective CNN architectures for accurately classifying images in the CIFAR-10 dataset. Five CNN architectures were implemented, namely [Architecture 1], [Architecture 2], [Architecture 3], [Architecture 4], and [Architecture 5] using the CIFAR-10 dataset. The architectures were selected based on the need to explore variations in convolutional filter sizes, dense layers, and batch normalization to assess their impact on CIFAR-10 image classification performance. Each architecture was trained on a standard training set and evaluated on a validation set. We used specific details on data preprocessing and training settings for a consistent and fair comparison. After training and evaluation, we have obtained the following results for each architecture. Architecture 1 has a training accuracy of 74.7% and validation accuracy of 76.6%, Architecture 2 has 96.09% and 86.08%, Architecture 3 has 77% and 78.1%, Architecture 4 has 67.91% and 69.54%, and Architecture 5 has 94.64% and 87.34% of training accuracy and validation accuracy respectively. After conducting a comparative analysis, we found that Architecture 5 has achieved the highest validation accuracy in classifying images in the CIFAR-10 dataset. These findings suggest that Architecture 5 is a promising choice for image classification tasks involving the CIFAR-10 dataset.

With the continuous development of artificial intelligence technology, the value of massive power data has been widely considered. Aiming at the problem of single-phase-to-ground fault line selection in resonant grounding system, a fault line selection method based on transfer learning depthwise separable convolutional neural network (DSCNN) is proposed. The proposed method uses two pixel-level image fusions to transform the three-phase current of each feeder into the RGB color image, which is used as the input of DSCNN. After DSCNN self-feature extraction, the fault line selection is completed. With the consideration that not all of power distribution systems can obtain a large amount of data in practical applications, the transfer learning strategy is adopted to transplant the trained line selection model. The smaller number of DSCNN parameters increases the portability of the model. The test results show that not only does the proposed method extracts obvious features, but also the line selection accuracy can reach 99.76%. It also has good adaptability under different sampling frequencies, different noise environments, and different distribution network topologies; the line selection accuracy can reach more than 97.43%.

The convolutional neural network (CNN) architecture has shown remarkable success in image classification and segmentation. Its popularity has increased promptly due to various factors such as exponential growth in computational resources, availability of benchmark datasets, supporting libraries, and open-source software. The efficiency of CNN architecture majorly depends on the complexity of the architecture, availability of datasets, and hyperparameter selection. But, due to the huge number of parameters in CNN architecture, its selection has completely remained ad hoc in the past works. In this article, a novel encoding technique has been proposed that can represent complex CNN architecture effectively. The article defines basic building blocks to represent CNN architecture such as the genesis block, transit block, agile block, and output block. This encoding structure is used to generate dynamic length chromosome structure and initialized using evolutionary algorithms. A comparative analysis is also presented that shows compared its effectiveness with existing encoding representations on the basis of the number of encoding parameters, training cost, and efficiency.

Online fault detection in industrial machinery, such as induction motors or their components (e.g., bearings), continues to be a priority. Most commercial equipment provides general measurements and not a diagnosis. On the other hand, commonly, research works that focus on fault detection are tested offline or over processors that do not comply with an online diagnosis. In this sense, the present work proposes a system based on a proprietary field programmable gate array (FPGA) platform with several developed intellectual property cores (IPcores) and tools. The FPGA platform together with a stray magnetic flux sensor are used for the online detection of faults in the outer race of bearings in induction motors. The integrated parts comprising the monitoring system are the stray magnetic flux triaxial sensor, several developed IPcores, an embedded processor for data processing, and a user interface where the diagnosis is visualized. The system performs the fault diagnosis through a statistical analysis as follows: First, a triaxial sensor measures the stray magnetic flux in the motor’s surroundings (this flux will vary as symptoms of the fault). Second, an embedded processor in an FPGA-based proprietary board drives the developed IPcores in calculating the statistical features. Third, a set of ranges is defined for the statistical features values, and it is used to indicate the condition of the bearing in the motor. Therefore, if the value of a statistical feature belongs to a specific range, the system will return a diagnosis of whether a fault is present and, if so, the severity of the damage in the outer race. The results demonstrate that the values of the root mean square (RMS) and kurtosis, extracted from the stray magnetic field from the motor, provide a reliable diagnostic of the analyzed bearing. The results are provided online and displayed for the user through interfaces developed on the FPGA platform, such as in a liquid crystal display or through serial communication by a Bluetooth module. The platform is based on an FPGA XC6SLX45 Spartan 6 of Xilinx, and the architecture of the modules used are described through hardware description language. This system aims to be an online tool that can help users of induction motors in maintenance tasks and for the early detection of faults related to bearings.

Some algorithms benefit from a hardware digital logic implantation to achieve higher speed or to meet specific timing requirements, such as in digital signal processing, digital communication, and also when investigating hardware-accelerated machine learning algorithms. We present an extensible, miniature, battery-operated Field Programmable Gate Array (FPGA) platform for wearable computing and IoT research, based on an Intel MAX10 FPGA. The platform is 30x30mm in size and can be used as a standalone device, or as an extension to a similarly sized microcontroller board, for example to pre-process high-speed data streams in hardware prior to relaying the data to a conventional processor. We present the FPGA board and characterise power consumption, resource usage, and processing speed for the implementation of elementary DSP operations, notably FIR filters. We also carry out a direct comparison of these metrics for the FIR algorithm running on an ARM Cortex M4 processor as well as a soft-core processor synthesized on the FPGA board. The results show that this miniature FPGA platform has sufficient logic gates and computing power for a wide class of digital communication algorithms. The platform hardware and firmware is available on GitHub.

In recent years, the current trend of Convolutional Neural Networks (CNNs) is toward lower computational cost to achieve lightweight. In lightweight convolutional neural networks, the depthwise separable convolution (DSC) is becoming the mainstream method. But in DSC, the pointwise convolution (PWC) with $1\times 1$ filters still has abundant parameters and computation. In this paper, an more efficient convolution algorithm is proposed to replace PWC, named kernel shared group convolution (KSGC). KSGC is used to combine channel information, which can be seen as the same convolution kernel sliding on the channel. In addition, Winograd algorithm is used to mitigate the number of multiplications required by KSGC in this paper. A CNN accelerator using a novel processing element (PE) performs 1-D Winograd in KSGC was implemented on a Ultra96-V2 field-programmable gate array (FPGA).At 200MHz clock frequency, the accelerator achieved computational performance of 52. 7GOPS and performance-power ratio of 10.42GOPS/W.

The sparse matrix vector product (SpMV) is a fundamental operation in multiple scientific algorithms, because it is generally the most computationally expensive stage. For this reason, numerous efforts have been made to optimize such operation on various hardware platforms. There is a growing concern in the high-performance computing world about power consumption, making energy efficiency an extremely important quality when evaluating hardware platforms. Due to their greater energy efficiency, Field-Programmable Gate Arrays (FPGAs) are available today as an interesting alternative to other hardware platforms for the acceleration of this type of operations. Our study focuses on the development of efficient kernels for the resolution of SpMV, measuring the achievable performance with respect to the hardware capabilities. In order to do so, we developed experiments that evaluate the peak performance of our platforms and based on the results we implemented optimized kernels for the calculation of SpMV. The tests were performed on Xilinx’s Alveo U50 platform. Among the results obtained, we highlight the convenience of applying fine-grained parallelism (vectorization of the data path) versus the coarse-grained (replication of the computation unit), achieving improvements in the first case of 7.7× compared to the second. We also observed that, in most cases, the FPGA platform provides higher energy efficiency than a traditional CPU, reaching a maximum of 3×.

Recognition of human activity based on convolutional neural network has received the interest of researchers in recent years due to its significant improvement in accuracy. A large number of algorithms based on the deep learning approach have been proposed for activity recognition purpose. However, with the increasing advancements in technologies having limited computational resources, it needs to design an efficient deep learning-based approaches with improved utilization of computational resources. This paper presents a simple and efficient 2-Dimensional convolutional neural network (2-D CNN) architecture with very small size convolutional kernel for human activity recognition. The merit of the proposed CNN architecture over standard deep learning architectures is fewer trainable parameters and lesser memory requirement which enables it to train the proposed CNN architecture on low GPU memory-based devices and also works well with smaller as well as larger size datasets. The proposed approach consists of mainly four stages: namely (1) creation of dataset and data augmentation, (2) designing 2-D convolutional neural network (CNN) architecture, (3) the proposed 2-D CNN architecture trained from scratch up to optimum stage, and (4) evaluation of the trained 2-D CNN architecture. To illustrate the effectiveness of the proposed architecture several extensive experiments are conducted on three publicly available datasets, namely IXMAS, YouTube, and UCF101 dataset. The results of the proposed method and its comparison with other state-of-the-art methods [8-12,14,18-26,29-33] demonstrate the usefulness of the proposed method.

Deep neural networks (DNNs) are widely used in human activity recognition (HAR). Compared to traditional HAR, embedded real-time HAR offers portability, low latency, and low power consumption. U-Net-based models enhance feature fusion and temporal resolution but face deployment challenges due to high complexity. This study proposes a hardware-accelerated U-Net++ inference model for embedded HAR. The U-Net++ enables network pruning for resourcelimited devices, and quantization converts FLOAT32 parameters to INT8 format for efficient execution. Implemented on a field programmable gate array (FPGA) device, the design optimizes digital signal processor (DSP) utilization via multiplexing and enhances data bandwidth using on-chip block RAM and FIFO-based weight caching. Validated on a Xilinx FPGA, the design achieves 99.0% and 96.6% accuracy on the WISDM and PAMAP2 datasets, respectively, using 39590 lookup tables, 35707 flip-flops, and 400 DSPs. Working at 267 MHz, it achieves <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$330 \mu$</tex> s inference latency and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$25.78 \text{GOPS} / \mathrm{W}$</tex> energy efficiency, supporting configurable input channels and network parameters across various FPGA platforms.

Convolution Neural Networks (CNNs) are responsible for the major discoveries in image classification and they are considered as the core of most current computer vision systems. In the implementation of deep CNN, Field-Programmable Gate Arrays (FPGAs) offer a promising paradigm towards major leaps in computational performance while achieving high-energy efficiency. Although current CNN accelerations on FPGA have demonstrated good performance, one major issue is that previously proposed implementation do not achieve a good balance between latency, precision, and hardware complexity. In order to overcome this problem, this paper proposes a highly optimized FPGA implementation of a CNN, named NASH-CNN (Neuro-inspired ArchitectureS in Hardware for CNN). An application for handwritten digit recognition, based on MNIST dataset, is evaluated. The experiment shows that our implementation achieves better performance/accuracy/complexity balance when compared to previously proposed schemes.

This paper explores real-time Convolutional Neural Network inference on Field Pro- grammable Gate Arrays (FPGAs) implemented in Synchronous Message Exchange (SME). We compare SME to the widespread FPGA tool, High-Level Synthesis (HLS), and com- pare both the SME and HLS implementations of CNNs with the PyTorch implementation for CNN on CPU/GPU. We find that the SME implementation is more flexible than the HLS implementation as it allows for more customization of the hardware. Programming with SME is more difficult than HLS, although easier than traditional Hardware Descrip- tion Languages. Finally, for a test use case, we find that the SME implementation on FPGA is approximately 2.8/1.4/2.0 times more energy efficient than CPU/GPU/ARM at larger batch sizes, with the HLS implementation on FPGA falling in between CPU/ARM and GPU in terms of energy efficiency. At a batch size of 1, appropriate for edge-device inference, the gap in energy efficiency between the FPGA and CPU/GPU/ARM imple- mentations becomes more pronounced, with the SME implementation on FPGA being approximately 83/47/8 times more energy efficient than the CPU/GPU/ARM implemen- tations, and with the HLS implementation on FPGA being approximately 40/23/4 times more energy efficient than the CPU/GPU/ARM implementations.

Convolutional neural networks (CNNs) are now often used in deep learning and computer vision applications. Its convolutional layer accounts for most calculations and should be computed fast in a local edge device. Field‐programmable gate arrays (FPGAs) have been adequately explored as promising hardware accelerators for CNNs due to their high performance, energy efficiency, and reconfigurability. This paper developed an efficient FPGA‐based 16‐bit fixed‐point hardware accelerator unit for deep learning applications on the 32‐bit low‐memory edge device (PYNQ‐Z2 board). Additionally, singular value decomposition is applied to the fully connected layer for dimensionality reduction of weight parameters. The accelerator unit was designed for all five layers and employed eight processing elements in convolution layers 1 and 2 for parallel computations. In addition, array partitioning, loop unrolling, and pipelining are the techniques used to increase the speed of calculations. The AXI‐Lite interface was also used to communicate between IP and other blocks. Moreover, the design is tested with grayscale image classification on MNIST handwritten digit dataset and color image classification on the Tumor dataset. The experimental results show that the proposed accelerator unit implementation performs faster than the software‐based implementation. Its inference speed is 89.03% more than INTEL 3‐core CPU, 86.12% higher than Haswell 2‐core CPU, and 82.45% more than NVIDIA Tesla K80 GPU. Furthermore, the throughput of the proposed design is 4.33GOP/s, which is better than the conventional CNN accelerator architectures.