Hardware-software partitioning and pipelined scheduling of transformative applications

One of the addressable problem in the hardware software co-design is partitioning of functionality on CPU and ASIC/FPGA. The partitioning phase requires the decision for mapping and scheduling of application given as task graphs on a given CPU/ASIC combination. Hardware software partitioning is one of the critical steps to decide which components can be implemented in hardware and which ones implemented in software so that overall system is optimized. Based on a task graph model, this paper presents the optimum solution of problem using genetic algorithm techniques. Experimental results demonstrate that this method can achieve optimized partitioning in terms of cost and delay. A trade off between cost and delay has also been achieved to get the best possible solution.

Embedded systems have a wide range as they have become essential parts of modern life. A typical embedded system consists of application-specific hardware and programmable software. Hardware-software (HW/SW) partitioning problem defines which tasks should be mapped to software and hardware. It allows the proposition of an optimised system with predefined constraints. In this paper, a heuristic algorithm, the hybrid-bee-colony-optimisation for multiple-choice HW/SW partitioning is proposed. The proposed algorithm aims to minimise power consumption and execution time, while meeting area constraint. This heuristic algorithm is developed to generate an approximate solution in acceptable delay. The Virtex 5 is chosen as a target platform. Simulation results are compared with existing works and they show rapidity with the generation of an optimal solution near to the exact one.

Applications that process continuous streams of data, e.g., sensor signals, video images, network packets, etc. are well-suited for pipelined execution on multicore processors. In many cases, however, the applications are subject to real-time constraints, especially in embedded systems. Besides maximizing the throughput, it is therefore important to minimize deviations in the timing. To solve this problem, we propose a method for self-timed scheduling and parallel execution of stream-based applications in soft real-time environments. Our experimental results show significantly lower latencies compared to state-of-the-art approaches, while achieving high throughput.

Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is the use of sleep transistors as power-gating elements to cut-off sub-threshold leakage current in circuits when they are in stand-by mode. Although sleep transistor insertion is very effective in cutting-off leakage, it also incurs timing, area and routing overhead. Since most of the sleep transistor insertion methodologies do post layout insertion, care should be taken such that there is minimal perturbation of the original layout. Over design of sleep transistors cells and sub-optimal sleep transistor placement must be avoided to achieve final design closure. Since the sleep transistor area plays an important and prominent role in this aspect, it necessitates for optimal sleep transistor sizing and synthesis technique under area constraints. In this paper, we first provide a methodology for optimal sleep transistor synthesis under given area constraints. We then apply our technique to the general timing and area constraint driven row-based power-gating methodology proposed in [13] and show how optimal low leakage designs with constraints on timing and area can be designed.

ENERGY efficient computing used to be a concern only for designers of untethered computer and mobile communication systems, where battery size and recharge intervals limited their usefulness. In the past few years, the importance of reducing energy has become a central concern for designers of tethered computers as well because of the power limitations of a standard household power outlet and because they are often deployed in large groups, in the case of server farms. To address the research issues that arise in energy efficient computing, the US Defense Advanced Projects Agency began a program several years ago under the heading Power Aware Computing and Communications (PAC/C). This has led to a wide range of new developments in energy efficient computing and communications. This special issue solicited original papers from, but not restricted to, researchers in the PAC/C program. Our goal was to show the wide range of computer related research that is concerned with minimizing energy consumption in one way or another. Our lead-off paper, “Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages,” employs genetic algorithm for module selection and scheduling under the constraints of power and area. The next paper, “Charge-Recovery Computing on Silicon,” presents an overview of energy-recovering systems, focusing on recent developments. The third paper, “A Holistic Approach to Designing Energy-Efficient Cluster Interconnects,” looks at interconnecting networks of computers and addresses the problem of designing the interconnects to be energy-efficient. The fourth paper, “Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors,” focuses on the microarchitectural level and proposes and analyzes a clustered loop buffer for VLIW-style processors. The analysis shows that such buffers are able to generate a significant amount of energy savings. The fifth paper in our series, “Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors,” moves to a higher level of abstraction and proposes a fast and efficient approach for designing and estimating energy consumption for single chip heterogeneous multiprocessors—a common platform for mobile system. The sixth paper, “An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs,” returns to the microarchitectural level. It proposes a design time instruction set minimization to reduce instruction cache power. The seventh paper, “Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations,” looks at the application level, specifically the power-performance of motion detection in an image processing application. The eighth paper, “Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes,” is a tutorial paper on sensor networks with special emphasis on their power requirements. The penultimate paper, “A Speculative Control Scheme for an Energy-Efficient Banked Register File,” again returns to the microarchitectural level and shows how low power register files can be constructed from smaller faster banks of registers. The last paper, “GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks,” proposes an adaptive scalable architecture targeted toward algorithm-specific tasks in which power is a constraint. The architectural model derives its scalability from a set of Globally Asynchronous and Locally Synchronous (GALS) building blocks.

Leakage power has become a serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a small penalty in performance. This paper focuses on leakage power reduction through automatic insertion of sleep transistors for power-gating. In particular, we propose a novel, layout-aware methodology that facilitates sleep transistor insertion and virtual-ground routing on row-based layouts. We also introduce a clustering algorithm that is able to handle simultaneously timing and area constraints, and we extend it to the case of multi- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vt</i> sleep transistors to increase leakage savings. The results we have obtained on a set of benchmark circuits show that the leakage savings we can achieve are, by far, superior to those obtained using existing power-gating solutions and with much tighter timing and area constraints.

The performance of pipelined datapath implementations is measured basically by three parameters: the clock cycle length, the initiation interval between successive iterations (inverse of the throughput) and the iteration time (turn-around time). In this paper we present a new method for computing performance bounds of pipelined implementations: The method has a low complexity and it handles behavioral specifications containing loop statements with interiteration data dependency and timing constraints.

Software pipelining increases the loop execution throughput by overlapping the execution of successive iterations in a pipelined fashion. For loops with control flows, software pipelining is not straightforward because we need to consider the overlap of more than one execution path. Modulo scheduling simply transforms them into straight-line loops through if-conversion which, in effect, achieves a fixed, worst-case initiation interval (II) among all paths. All-path pipelining (APP) and enhanced pipeline scheduling (EPS) can achieve a variable II depending on the path that is followed through the loop at execution time. Unfortunately, APP concentrates only on the overlap within the same path, entirely losing the overlap between different paths, whereas EPS attempts to overlap all future paths together, failing to produce a tight schedule for each individual path. In this paper, we propose a new approach to EPS which splits each individual path in the loop via tail duplication, and performs EPS in a way to guarantee a tight schedule within the same path, while producing a comparable cross-path schedule. Our experimental results indicate that the proposed technique can achieve as much as a geometric mean of 7% performance improvement on non-trivial integer benchmarks.

A formal methodology for automatic hardware-software partitioning and co-scheduling between the muP and the FPGA has not yet been established. Current work in automatic task partitioning and scheduling for reconfigurable systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. In this work, we consider the problem of co-scheduling task graphs on reconfigurable systems. The target systems have an execution model which allows any subtask that can run on the FPGA to also run on the microprocessor, and allows reconfigurability of the FPGA (subject to area, performance, resource, and timing constraints). In this paper, we introduce a methodology for automatic co- scheduling using a proposed heuristic algorithm for hardware/software co-scheduling, ReCoS. It will be shown that the proposed algorithm provides up to an order of magnitude improvement in scheduling and execution times when compared with hardware/software co-schedulers found in related fields such as embedded systems, heterogeneous systems, and reconfigurable hardware systems.

SAGAPA (System Architecture Generated from A Parallel Algorithm) is an image processing system design tool based on an original methodology that automatically carries out the minimal architecture adapted to the application algorithm in respect with a maximal execution time constraint. The obtained architecture is minimal in terms of number of processors, amount of memory, and complexity of interconnection network. An execution-driven type simulation is performed in order to estimate resource's utilization and to check the time constraint.

Fault-tolerance is emerging as one of the important optimization objectives for designs in deep submicron technology nodes. This paper proposes a technique of application mapping and scheduling with checkpointing on a multiprocessor system to maximize the reliability considering transient faults. The proposed model incorporates checkpoints with imperfect fault detection probability, and pipelined execution and cyclic dependency associated with multimedia applications. This is solved using an Artificial Intelligence technique known as Particle Swarm Optimization to determine the number of checkpoints of every task of the application that maximizes the confidence of the output. The proposed approach is validated experimentally with synthetic and real-life application graphs. Results demonstrate the proposed technique improves the probability of correct result by an average 15% with imperfect fault detection. Additionally, even with 100% fault detection, the proposed technique is able to achieve better results (25% higher confidence) as compared to the existing fault-tolerant techniques.

Focus on software

SummaryThe divisible load scheduling of image processing applications on the heterogeneous star and multi‐level tree networks is addressed in this paper. In our platforms, processors and network links have different speeds. In addition, computation and communication overheads are considered. A new genetic algorithm for minimizing the processing time of low‐level image applications using divisible load theory is introduced. The closed‐form solution for the processing time, the image fractions that should be allocated to each processor, the optimum number of participating processors, and the optimal sequence for load distribution are derived. The new concept of equivalent processor in tree network is introduced and the effect of different image and kernel sizes on processing time and speed up are investigated. Finally, to indicate the efficiency of our algorithm, several numerical experiments are presented.

High-level synthesis tools are increasingly adopted for designing complex applications on FPGAs. These tools necessitate fast and accurate estimation of FPGA resources in order to produce good design solutions while minimizing design time. Multiplication operations are very commonly found in signal processing, communication, video and image processing applications. In this paper, we present a rapid technique to estimate DSPs utilization for different types of multiplication operations during high-level synthesis. The proposed technique models the synthesis inferences and optimizations performed by state-of-the-art FPGA design tool in order to reliably estimate the number of DSPs and associated LUTs cost of multiplication operations.

In this paper we have proposed different design techniques for the Goertzel Algorithm for dual tone multi-frequency (DTMF) detection. We have proposed parallel and sequential designs depending on the constraints of timing and area respectively. The optimized implementations have been realized on Spartan-6 FPGA device and take 1.89us in parallel architecture and 13.71us in sequential architecture to decode a number. The design is efficient in terms of resources consumed as well, consuming less than 1% of LUTs. Comparison with the prior implemented designs is shown in the results section.