Lower bounds on the iteration time and the initiation interval of functional pipelining and loop folding

Many present-day microprocessors have fine grain parallelism, be it in the form of a pipeline, of multiple functional units, or replicated processors. The efficient use of such architectures depends on the capability of the compiler to schedule the execution of the object code in such a way that most of the available hardware is in use while complying with data dependences. In the case of one simple loop, the schedule may be expressed as an affine form in the loop counter. The coefficient of the loop counter in the schedule is the initiation interval, and gives the mean rate at which loop bodies may be executed. The dependence constraints may be converted to linear inequalities in the coefficients of a closed form schedule, and then solved by classical linear programming algorithms. The resource constraints, however, translate to non-linear constraints. These constraints become linear if the initiation interval is known. This leads to a fast searching algorithm, in which the initiation interval is increased until a feasible solution is found.

In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (II), allowing to overlap subsequent iterations. The problem is to find the smallest II and corresponding operation schedule that fulfils all data dependencies and resource constraints, both of which are usually found by modulo scheduling.We propose Moovac1, a novel integer linear program (ILP) formulation of the modulo scheduling problem based on overlap variables to model exact resource constraints. Given enough time, Moovac will find a mimimum-II solution. This is in contrast to Canis' state-of-the-art Modulo SDC approach, which requires heuristic simplifications of the resource constraints. Moovac can thus be used as a reference to evaluate heuristics, or in a time-limited mode as a heuristic itself to provide a best-so-far solution.We schedule kernels from the CHStone and MachSuite benchmarks for loop pipelining with Moovac, Modulo SDC and a prior exact formulation by Eichenberger.Moovac has competitive performance in its time-limited mode, and delivers better results faster than the Modulo SDC scheduler for some loops. Often its structure leads to quicker solution times than Eichenberger's formulation.Using the Moovac-computed optimal solutions as a reference, we can confirm that the Modulo SDC heuristic is indeed capable of finding optimal or near-optimal solutions for the majority of small- to medium-sized loops. However, for larger loops the two algorithms begin to diverge, with Moovac often being significantly faster to prove the infeasibility of a candidate II. This can be exploited by running both schedulers synergistically, leading to a quicker convergence to the final II.

This paper presents several theoretical and fundamental results on the register need in periodic schedules, also known as MAXLIVE. Our first contribution is a novel formula for computing the exact number of registers needed by a scheduled loop. This formula has two advantages: Its computation can be done by using a polynomial algorithm with O(n lg n) complexity (n is the number of instructions in the loop) and it allows the generalization of a previous result [13]. Second, during software pipelining, we show that the minimal number of registers needed may increase when incrementing the initiation interval (II), which is contrary to intuition. For the case of zero architectural delays in accessing registers, we provide a sufficient condition for keeping the minimal number of registers from increasing when incrementing the II. Third, we prove an interesting property that enables us to optimally compute the minimal periodic register sufficiency of a loop for all its valid periodic schedules, irrespective of II. Fourth and last, we prove that the problem of optimal stage scheduling under register constraints is polynomially solvable for a subclass of data dependence graphs, whereas this problem is known to be NP-complete for arbitrary dependence graphs [7]. Our latter result generalizes a previous achievement [13] which addressed data dependence trees and forest of trees. In this study, we consider cyclic data dependence graphs without taking into account any resource constraints. The aim of our theoretical results on the periodic register need is to help current and future software pipeliners achieve significant performance improvements by making better (if not the best) use of the available resources.

Transformative applications are computation intensive applications characterized by iterative dataflow behavior. Typical examples are image processing applications like JPEG, MPEG, etc. The performance of embedded hardware-software systems that implement transformative applications can be maximized by obtaining a pipelined design. We present a tool for hardware-software partitioning and pipelined scheduling of transformative applications. The tool uses iterative partitioning and pipelined scheduling to obtain optimal partitions that satisfy the timing and area constraints. The partitioner uses a branch and bound approach with a unique objective function that minimizes the initiation interval of the final design. We present techniques for generation of good initial solution and search-space limitation for the branch and bound algorithm. A candidate partition is evaluated by generating its pipelined schedule. The scheduler uses a novel retiming heuristic that optimizes the initiation interval, number of pipeline stages, and memory requirements of the particular design alternative. We evaluate the performance of the retiming heuristic by comparing it with an existing technique. The effectiveness of the entire tool is demonstrated by a case study of the JPEG image compression algorithm. We also evaluate the run time and design quality of the tool by experimentation with synthetic graphs.

This paper introduces a new static data dependence constraint, called dependence difference inequality, which can deal with coupled subscripts for multi-dimensional array references. Unlike direction vectors, dependence difference inequalities are related to not only the iteration space for a loop program but also the operation distance between two operations. They are more strict than other methods, and can act as additional constraints to each variable in a linear system on their own or with others. As a result, the solution space for a linear system can be compressed heavily. So long as dependence difference inequalities do not satisfy simultaneously, the loop can be software-pipelined with any initiation interval even if there exists a data dependence between two operations. Meanwhile, by replacing direction vectors with dependence difference inequalities some conservative estimations made by other traditional data dependence analysis approaches can be eliminated.

A quantum realization of the generalized Arnold transform is designed. A novel quantum image encryption algorithm based on generalized Arnold transform and double random-phase encoding is proposed. The pixels are scrambled by the generalized Arnold transform, and the gray-level information of images is encoded by the double random-phase operations. The keys of the encryption algorithm include the independent parameters of coefficients matrix, iterative times and classical binary sequences, and thus, the key space is extremely large. Numerical simulations and theoretical analyses demonstrate that the proposed algorithm with good feasibility and effectiveness has lower computational complexity than its classical counterpart.

Software pipelining increases the loop execution throughput by overlapping the execution of successive iterations in a pipelined fashion. For loops with control flows, software pipelining is not straightforward because we need to consider the overlap of more than one execution path. Modulo scheduling simply transforms them into straight-line loops through if-conversion which, in effect, achieves a fixed, worst-case initiation interval (II) among all paths. All-path pipelining (APP) and enhanced pipeline scheduling (EPS) can achieve a variable II depending on the path that is followed through the loop at execution time. Unfortunately, APP concentrates only on the overlap within the same path, entirely losing the overlap between different paths, whereas EPS attempts to overlap all future paths together, failing to produce a tight schedule for each individual path. In this paper, we propose a new approach to EPS which splits each individual path in the loop via tail duplication, and performs EPS in a way to guarantee a tight schedule within the same path, while producing a comparable cross-path schedule. Our experimental results indicate that the proposed technique can achieve as much as a geometric mean of 7% performance improvement on non-trivial integer benchmarks.

Article history: Received July 10, 2011 Received in Revised form October, 12, 2011 Accepted 18 December 2011 Available online 24 December 2011 This paper tackles the single machine scheduling problem with dependent setup time and precedence constraints. The primary objective of this paper is minimization of total weighted tardiness. Since the complexity of the resulted problem is NP-hard we use metaheuristics method to solve the resulted model. The proposed model of this paper uses genetic algorithm to solve the problem in reasonable amount of time. Because of high sensitivity of GA to its initial values of parameters, a Taguchi approach is presented to calibrate its parameters. Computational experiments validate the effectiveness and capability of proposed method. © 2012 Growing Science Ltd. All rights reserved.

For safety-critical real-time software, if worst-case execution time (WCET) violates a time constraint, it is considered having a timeliness defect. To fix the defect early with lower cost, a WCET optimization strategy is proposed based on source code refactoring. The strategy guides programmers to search refactoring opportunities in the correct positions and perform refactorings by a reasonable sequence. To this end, the worst-case execution path (WCEP) of a target program is firstly extracted from its control flow graph. Then the WCEP is mapped onto source code by the back-annotation technique. An abstract syntax tree-based invariant path identification algorithm is developed for recognizing the invariant paths from the source-level WCEP. According to the invariant paths and loop statements, the source code is divided into four optimization regions with different priorities. Thus the searching scopes are reduced, and invalid refactorings are avoided. On the basis, the refactoring which has the lowest cost in the same region is performed first. To support the strategy, a cost model of source code refactoring is designed. It mainly considers adverse effects of refactorings on the maintainability of source code. The experimental results showed that the optimization strategy reduced WCET effectively and maximally kept the maintainability. Therefore it is more suitable for WCET optimization in an early programming phase. It is helpful to fix the defects early and then guarantee the timeliness safety of the software.

Cloud computing has emerged as a promising platform to execute scientific workflows. The size of such workflows could reach up to thousands of tasks, which have data dependency constraints. Accordingly, optimising the utilisation of the used resources is an essential factor in reducing the execution time and cost. This paper presents a Utility-based Algorithm (UBA) that works by assigning tasks to VMs based on a utility function that aims to minimise the execution cost and time. The results showed that the UBA had a significant impact on reducing the execution cost and makespan.

Embedded systems have strict timing and code size requirements. Retiming is one of the most important optimization techniques to improve the execution time of loops by increasing the parallelism among successive loop iterations. Traditionally, retiming has been applied at instruction level to reduce cycle period for single loops. While multi-dimensional (MD) retiming can explore the outer loop parallelism, it introduces large overheads in loop index generation and code size due to loop transformation. In this paper, we propose a novel approach, that combines iterational retiming with instructional retiming to satisfy any given timing constraint by achieving full parallelism for iterations in a partition with minimal code size. The experimental results show that combining iterational retiming and instructional retiming, we can achieve 37% code size reduction comparing to applying iteration retiming alone.

Patronizing and condescending language (PCL) can find its way into many mediums of public discourse. Presence of PCL in text can produce negative effects in the society. The challenge presented by the task emerges from the subtleties of PCL and various data dependent constraints. Hence, developing techniques to detect PCL in text, before it is propagated is vital. The aim of this paper is twofold, a) to present systems that can be used to classify a text as containing PCL or not, and b) to present systems that assign the different categories of PCL present in text. The proposed systems are primarily rooted in transformer-based pre- trained language models. Among the models submitted for Subtask 1, the best F1-Score of 0.5436 was achieved by a deep learning based ensemble model. This system secured the rank 29 in the official task ranking. For Subtask 2, the best macro-average F1-Score of 0.339 was achieved by an ensemble model combining transformer-based neural architecture with gradient boosting label-balanced classifiers. This system secured the rank 21 in the official task ranking. Among subsequently carried out experiments a variation in architecture of a system for Subtask 2 achieved a macro-average F1-Score of 0.3527.

Existing global microcode compaction algorithms have all been based on the assumption that the parallelism exploitation is constrained only by data dependency and resource limitation. However, the timing constraint also has great impact upon microcode compaction, thus it is highly necessary to study global microcode compaction under timing constraints. This paper conducts an analysis on the global timing problem, modifies the MO motion rules and presents an algorithm based on Trace Scheduling for global microcode compaction under timing constraints.

Modern Advanced Driver-Assistance Systems (ADAS) combine critical real-time and non-critical best-effort tasks and messages onto an integrated multi-core multi-SoC hardware platform. The real-time safety-critical software tasks have complex interdependencies in the form of end-to-end latency chains featuring, e.g., sensing, processing/sensor fusion, and actuating. The underlying real-time operating systems running on top of the multi-core platform use static cyclic scheduling for the software tasks, while the communication backbone is either realized through PCIe or Time-Sensitive Networking (TSN). In this paper, we address the problem of configuring ADAS platforms for automotive applications, which means deciding the mapping of tasks to processing cores and the scheduling of tasks and messages. Time-critical messages are transmitted in a scheduled manner via the timed-gate mechanism described in IEEE 802.1Qbv according to the pre-computed Gate Control List (GCL) schedule. We study the computation of the assignment of tasks to the available platform CPUs/cores, the static schedule tables for the real-time tasks, as well as the GCLs, such that task and message deadlines, as well as end-to-end task chain latencies, are satisfied. This is an intractable combinatorial optimization problem. As the ADAS platforms and applications become increasingly complex, such problems cannot be optimally solved and require problem-specific heuristics or metaheuristics to determine good quality feasible solutions in a reasonable time. We propose two metaheuristic solutions, a Genetic Algorithm (GA) and one based on Simulated Annealing (SA), both creating static schedule tables for tasks by simulating Earliest Deadline First (EDF) dispatching with different task deadlines and offsets. Furthermore, we use a List Scheduling-based heuristic to create the GCLs in platforms featuring a TSN backbone. We evaluate the proposed solution with real-world and synthetic test cases scaled to fit the future requirements of ADAS systems. The results show that our heuristic strategy can find correct solutions that meet the complex timing and dependency constraints at a higher rate than the related work approaches, i.e., the jitter constraints are satisfied in over 6 times more cases, and the task chain constraints are satisfied in 41% more cases on average. Our method scales well with the growing trend of ADAS platforms.

Dataflow dominated embedded systems often use data flow graphs (DFG) as system models. To achieve the desired performance, these systems usually contain a lot of hardware/software components working in parallel. These concurrent and cooperative components result in the contentions for shared resources due to architecture and data dependencies. The approach to solve the contentions can be priority assignments. In this paper we introduce an algorithm which can find out a priority assignment for a given set of components working in parallel with a timing constraint. In addition, the algorithm also provides a fast way to calculate, whether a set of components working in parallel can guarantee a given timing constraint. Hence the algorithm can be applied both in designing phase and implementation phase of hardware/software co-design for embedded systems.