Heterogeneous Integration of Diamond Electronics: Transistors, Diodes, and Packaging

III-Nitrides promise to offer high-frequency power amplifiers at higher power densities. This is attractive for realizing device platforms for 5G and beyond. It also enables integrating Si-based electronics to complement functionalities. However, to obtain the full potential of III-Nitrides one must operate these transistors at higher power densities, for which thermal management is crucial.Due to the continuous need for higher performance in various applications ranging from DC to W-band frequencies, semiconductor devices are pushed to higher power densities. This results in a higher junction temperature owing to the Joule heating in the channel resulting in device performance degradation and premature failure. Using devices based on wide-bandgap (WBG) semiconductors such as Gallium Nitride (GaN) and Gallium Oxide (GaOx) with a larger critical electric field and high-temperature tolerance, one could increase the power density. However, in order to increase the output power to the levels that is promised by these wide bandgap materials, junction temperature reduction through device-level cooling is critical. We are actively researching thermal management at device, circuit and packaging level using synthetic polycrystalline (PC) diamond. PC-diamond, at an appropriate grain size offers a TC is higher than any competing thermal vias with metals without interfering the electrical performance. Over the past 5 years we have demonstrated the potential of integrating diamond with GaN and recently achieving a record low diamond/GaN thermal boundary resistance (TBR) along with a relatively high diamond thermal conductivity (TC). This remarkable thermal performance was be achieved by maintaining the electrical performance, as demonstrated by the unharmed channel charge and mobility results.There are two key requirements for thermal management using heat spreading from the channel: first, a low thermal boundary resistance (TBR) between the hot spot in the channel and the heat spreader is required (in this study between GaN channel and diamond). Second, a low thermal resistance path to the heat-sink is crucial from the diamond layer which is directly proportional to diamond’s thermal conductivity (TC). In collaboration with Univ of Bristol, we have reported a TBR of ~3 m2K/GW, to date, known to be the lowest reported TBR for GaN HEMT technology. Diamond-GaN TBR depends strongly on the interface smoothness and the thickness of interfacial Si3N4 layer. A thinner Si3N4 resulted in lower TBR and allowed superior phonon coupling from the channel to the spreader. We have also measured a remarkably high TC for a 2 μm-thick diamond layer yielding over 650 W/m.K. The diamond grains are near isotropic in shape that allows excellent in-plane and cross-plane thermal conductivity. Achieving high TC within a thin film of diamond, grown heterogeneously, underscores the importance of our technique, since it reduces the residual stress when integrating with different materials that involves many thin layers like GaN/AlGaN HEMT epi-layers.β-Ga2O3 is an emerging ultra-wide bandgap material showing promises for both power and RF devices. However, the material’s low thermal conductivity poses to be a challenge for efficient power delivery (at any frequencies). PC diamond was successfully grown on (‾¯201)β-Ga2O3 using proper nucleation technique and thermal characterizations were conducted. A thermal conductivity (diamond + nucleation) and thermal boundary resistance at the diamond/β-Ga2O3 interface of 110 ± 33 W/mK and 30.2 ± 1.8 m2K/GW, respectively were measured.Our current results demonstrates a very promising roadmap for wide bandgap semiconductors via diamond integration.

Limitations of silicon (Si) based power electronic devices can be overcome with Silicon Carbide (SiC) because of its remarkable material properties. SiC is a wide bandgap semiconductor material with larger bandgap, lower leakage currents, higher breakdown electric field, and higher thermal conductivity, which promotes higher switching frequencies for high power applications, higher temperature operation, and results in higher power density devices relative to Si [1]. The proposed work is focused on design of a SiC gate driver to drive a SiC power MOSFET, on a Cree SiC process, with rise/fall times (less than 100 ns) suitable for 500 kHz to 1 MHz switching frequency applications. A process optimized gate driver topology design which is significantly different from generic Si circuit design is proposed. The ultimate goal of the project is to integrate this gate driver into a Toyota Prius plug-in hybrid electric vehicle (PHEV) charger module. The application of this high frequency charger will result in lighter, smaller, cheaper, and a more efficient power electronics system.

Summary form only given. Diamond has unique properties that make it an ideal material for use in a high power, high repetition rate switch, particularly for high temperature applications. Diamond has an extremely high electrical breakdown strength (/spl sim/10 MV/cm) which allows for high voltage switches in compact packages. Diamond is a very wide bandgap (5.5 eV) material. The wide bandgap not only reduces the leakage current but allows the fabrication of devices that are not semiconductor, junction type devices. Because diamond is not doped to act like a semiconductor, it switches from its normal insulator state to conducting state. This in turn permits bipolar conduction in diamond devices, another advantage over junction switches. In addition to these advantages, diamond's superior thermal properties and fast turn-on/turn-off make it well suited to high repetition rate, high power applications. The switch conducts when an electron beam or UV radiation is absorbed within the diamond. Conduction ceases upon the cessation of the incident radiation. A simple model has been developed that predicts the performance of UV triggered diamond switches with respect to efficiency, optimum current and optimum UV input power. This model predicts that for certain applications efficiencies of >130% can be obtained. Based on this model we have created a laser triggered diamond switch that produces 100 kV, 5 ns long pulses with a rise and fall time of <1 ns. Data from the 100 kV switch and model will be presented.

Wide bandgap materials are suitable for high power and high temperature applications. However, these materials must also transport heat from the active device regions effectively. Structural defects, chemical defects, and interface properties can degrade performance. Electron microscopy and x-ray scattering based techniques are employed to provide insight into the defects present in these materials. When these techniques are integrated with thermal transport measurements and theoretical insights gained from molecular dynamics simulations, a much better understanding of thermal transport in wide bandgap materials can be realized. Examples of how defects impact transport for diamond boundary interfaces, AlN layers, and GaN heterostructures will be presented.

The demands for increased data transmission rates and bandwidth as well as reduced signal loss are increasing while package size is getting bigger. To accommodate increasing package size and manage high frequency loss and warpage management, Glass substrates in advanced packaging are gaining momentum for heterogeneous integration of advanced semiconductor packaging. Based on Yole report in 2020, a 2.5-3 fold increase from 2019 to 2025 for the glass substrates is predicted. Glass core and Glass interposer could become a leading processing technology in advanced Panel Level Packaging (PLP). Cost effectiveness and high-frequency characteristics of glass laid strong pathways for Advanced Packaging Roadmaps. However, insertion of glass poses several challenges such as CD uniformity of Through Glass Via (TGV) etch over different aspect ratio of via sizes. Also due to the CTE mismatch between glass and metal, adhesion and stress management appears to be a huge issue for integration of TGV metallization and RDL layers. This paper presents the detail of TGV etch process with respect to different glass types, laser modification methods, and aspect ratio. Etching characterization over bath life as well as with various Design of Experiments (DOE) was performed to address the HVM challenges. Fabrication of TGV and metallization requires a good buffer layer (BL) on glass vias followed by Eless Cu deposition. Based on the types and properties of buffer layer, buffer layer serves the purpose of adhesion promotion liner (APL) as well as stress buffer layer (SBL). Additionally, Electrode less (Eless) Cu would be beneficial to provide as seed layer for conformal or full TGV metallization. Hence, a closer look into the development of Through Glass Via (TGV) processing, Adhesion promotion layer (APL), and Eless Cu techniques are discussed in this paper. A Wet process system has been developed to enable the TGV processing, Adhesion promotion, and Eless Cu for different types of glass substrates. Cross sectional and chemical analyses were done to validate the studies and the data were used to develop the glass etching, APL/SBL, and Eless Cu. Simulation and experimental data indicates that this approach is feasible to address glass processing and stress management challenges.

Polymer composites, with both high thermal conductivity and high electrical insulation strength, are desirable for power equipment and electronic devices, to sustain increasingly high power density and heat flux. However, conventional methods to synthesize polymer composites with high thermal conductivity often degrade their insulation strength, or cause a significant increase in dielectric properties. In this work, we demonstrate epoxy nanocomposites embedded with silver nanoparticles (AgNPs), and modified boron nitride nanosheets (BNNSs), which have high thermal conductivity, high insulation strength, low permittivity, and low dielectric loss. Compared with neat epoxy, the composite with 25 vol% of binary nanofillers has a significant enhancement (~10x) in thermal conductivity, which is twice of that filled with BNNSs only (~5x), owing to the continuous heat transfer path among BNNSs enabled by AgNPs. An increase in the breakdown voltage is observed, which is attributed to BNNSs-restricted formation of AgNPs conducting channels that result in a lengthening of the breakdown path. Moreover, the effects of nanofillers on dielectric properties, and thermal simulated current of nanocomposites, are discussed.

Wide bandgap (WBG) semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) offer higher switching speed, greater power density, and elevated operational temperature capabilities compared to silicon-based counterparts. However, conventional packaging technologies cannot fully leverage these benefits, necessitating innovative packaging strategies. This dissertation explores pressure contact technology (PCT) to enhance performance and reliability of highly integrated WBG power modules. Various interconnection approaches are evaluated for their suitability: fuzz buttons provide low parasitic inductance and flexibility for gate connections; graphene film (GF) elastomers offer compact size and high thermal conductivity; and metal sheet springs ensure robust power interconnections. A novel spring connector with low inductance (3 nH) and electrical resistance (5 mΩ) is utilized to connect substrates, enhancing heat dissipation and mechanical stability. The electro-thermal characteristics and reliability of pressure contact with molybdenum plates (PCMo) technology are compared with emerging die-attach technologies such as pressureless sintered Ag (SAg), pressure sintered Cu (PSCu), and commercial TO220 counterparts incorporating the same SiC chips. Experimental results demonstrate that PCMo introduces additional contact resistance (∼ 10 mΩ, 0.42 K/W) but exhibits superior power cycling reliability (∼ 6053 cycles) under a junction temperature from 50ºC to 200ºC due to the elimination of die-attach failures. Failure analysis identifies degradation and crack mechanisms in SAg, PSCu, and TO220 samples. Building on these insights, a 3D PCT-based half-bridge SiC module is developed using GF and fuzz buttons, achieving a low thermal resistance of 0.66 K/W, minimal parasitic inductance of 5.1 nH, and reduced voltage overshoot of 5.8%. For high-power applications, an eight-chip parallel SiC module with metal sheet springs demonstrates balanced current distribution and low inductance of 4.8 nH. The findings of this dissertation highlight the potential of PCT in improving the performance and reliability of heterogeneous integrated WBG power modules, particularly for high-power and high-temperature applications.

Relaxor regulation and improvement of energy storage properties of Sr2NaNb5O15-based tungsten bronze ceramics through B-site substitution

With the development of artificial intelligence (AI) and high-performance computing (HPC) technology, advanced packages such as CoWoS (Chip on Wafer on Substrate) have become more popular in recent years due to its outstanding signal transmission speed and space management efficiency. Nevertheless, such high-power applications and the large size of heterogeneous integrated package may lead to thermal and high package warpage problems. In that case, the high stiffness heat spreader is usually used to solve the problem of large warpage. However, structural damage caused by stress and additional thermal resistance from the interface between heat spreader and die top surface have occurred. In terms of stress and thermal issues, optimizing packaging material selection and high thermal conductivity thermal interface material (TIM) are widely used to reduce the stress risk and enhance thermal performance. Therefore, it is important to accurately predict mechanical stress performance and thermal behavior. In this study, the thermal conductivity that considers real application of TIM needs to be extracted to ensure the FO-EB-T (Fan-Out Embedded Bridge with TSV) package thermal performance. In order to achieve this purpose, junction-to-case thermal resistance (ӨJC) measurement of large lidded FCBGA thermal test vehicle (TTV) is firstly measured to ensure the silicon based/graphite/alloy based TIMs thermal performance with liquid-cooling test fixture. Scanning acoustic tomography (SAT) and destructive physical analysis (DPA) are measured to check the TIM coverage and bond line thickness (BLT). Then, thermal conductivity which considers the interface effect is calculated by heat transfer equation using ӨJC, TIM coverage and BLT results. After extracting the thermal conductivity from the TTV measurement, a thermal simulation is constructed to ensure thermal behavior of the large lidded FO-EB-T test vehicle with the liquid cooling system using FloTHERM. Finally, the mechanical performance of the FO-EB-T is simulated by ANSYS to check the warpage and stress behavior. The structural material optimization is proposed to ensure the package warpage performance while reducing the chip module epoxy molding compounds (EMC) stress risk. Overall, the paper proposes a method that can extract the thermal conductivity of TIMs in real application. And further ensure not only the thermal performance but also mechanical behavior of large lidded FO-EB-T by thermal and mechanical simulation. Above that, the FO-EB-T package development that can save the design of experiments (DOE) and the thermal behavior consider real application are being proposed.

The aspiration of electronic technologies that are resistant to high‐energy cosmic radiation is essential for current harsh radiation environment exploration. Integrated circuits mostly require post‐processing after designing, making their structures more complex than the standard systems. Thus, unique designs and strategies are developed to enable the high tolerance of space electronics to radiation in nuclear and avionic applications. The wide bandgap semiconductor (WBG) materials with excellent electronic/optical properties and structural stability are appealing options for radiation‐immune applications. Here, in this article, the development and fabrication of various electronic devices have been reviewed using different wide bandgap materials for radiation‐hardened applications. Detailed investigations are discussed, from the fundamental wide bandgap materials withstanding limited irradiation to the development processes of the electronic devices used in harsh environments. Furthermore, the challenges and future perspectives of the WBG‐based radiation harsh electronic devices are also highlighted in this review with commercial application in space stations and aircraft.

Significant waste heat generated in power electronics components such as inverters in EVs and hybrid vehicles due to the high power density, can cause material degradation. Further, constantly fluctuating power and torque demands in the electric drive train results in temperature gradients in the electronic components that exacerbate fatigue failures if thermal management is not addressed properly. Boron Nitride (BN) has one of the highest thermal conductivities coupled with excellent electrical insulation amongst ceramic fillers. Its low dielectric constant, dielectric loss, and high break down strength, along with its chemical inertness make it an attractive filler in thermal management applications pushing for higher power, higher voltages, and higher-speed transmissions, while maintaining lighter weight and smaller size. With push for higher voltage, coupled with increasing switching frequencies, dielectric loss can result in additional heat generation in the device. BNs low dielectric loss compared to other fillers enables good heat dissipation with very minimal energy loss.This work demonstrates providing improved thermal pathways for heat dissipation without fundamentally changing the package design by increasing thermal conductivity of the potting compound that encapsulates the dies. Pure resins such as silicones or epoxy-based systems are mostly used in these applications that provide protection from the elements, some mechanical support, but little thermal conductivity. The current work uses BN filled potting compounds that vastly improves thermal conductivity and can also improve stiffness of the resin while maintaining adequate compliance, providing additional mechanical support to the interconnects. Currently for single sided devices, heat generated is removed from the underside of the dies via a die-attach into a liquid or air-cooled substrate. This is the most efficient heat removal with the lowest thermal resistance (Rth). However, providing additional pathways through the potting compound enables heat extraction from top of the dies and interconnects/ wire bonds, spreading it to a larger area for improved heat dissipation.The current work describes a demonstrator device that mimics a liquid cooled single sided IGBT/ MOSFET device in terms of heat generation and cooling. Three different configurations were evaluated: (1) pure resin die attach and pure resin potting, (2) BN based thermally conductive die attach, but pure resin potting, which mimics most current single-side cooled devices, and (3) BN based thermally conductive die attach and thermally conductive potting.Multiple resistors (TO-247 thick film power resistor) were mounted on a water-cooled base plate with an epoxy based thermal interface material (TIM). A thermocouple was embedded to each resistor to monitor temperature during testing. Each resistor was compartmentalized with side walls to isolate them, providing equal area and coverage by the cold plate. They were then potted with different silicone based potting formulations to evaluate their effectiveness on device temperature. The temperature of the cold plate was kept constant at 25oC by a water-cooled chiller. The resistors were connected to a DC power supply and tested individually at different power levels. The results showed a 48% lower resistor temperature at max. power for the BN formulation compared with standard silicone potting between (2) and (3), dropping from 140oC to 84oC. This approach shows considerable promise of using BN based thermally conductive potting compound over standard silicone or epoxy systems. Boron nitrides high breakdown strength, chemical inertness, coupled with low loss make it an extremely attractive material for use in thermal management in power electronics in EV applications, maximizing the safety, performance, efficiency, and overall longevity of EVs.

Power devices are experiencing strong growth driven by demand in a variety of areas. Applications including energy generation and infrastructure, electric and hybrid vehicles, electric vehicle charging, datacenters, industrial automation, smart cities and buildings, home appliances, and transportation are driving demand for power devices. While many companies continue to expand production of silicon-based power devices, there is also demand for devices based on new wide band gap (WBG) materials such as silicon carbide (SiC) and gallium nitride (GaN). Driven by the need for increased power density and system efficiency, these WBG materials are being adopted in many applications and may require new packages, materials, and assembly methods. This presentation describes package trends and discusses some of the challenges faced.

Wide bandgap electronics made from nitrides (e.g., Gallium Nitride (GaN)) and oxides (e.g., Gallium Oxide (Ga2O3)) are currently under development due to their potential to create some of the most advanced RF and power electronic devices in the world. However, the thermal response of these devices under applied electric fields can create large power densities (RF and power electronics) that must be understood. For many of these devices, the electrothermal response plays a strong role in both the acceptable operation or long-term failure and reliability of the devices. Thus, tools that can help elucidate these responses and provide a method to help design better devices is of critical need for this field.In this talk we will discuss advancements in thermal characterization techniques that have allowed new insights into electrothermal behavior in GaN and Ga2O3 materials and devices. Specifically, a focus on the role of device architecture and material processing will be addressed. For GaN and Ga2O3 RF and power electronics, the role of thermal interfaces in the heat dissipation of both lateral and vertical device architectures will be discussed. We will cover aspects of semiconductor-semiconductor as well as metal-semiconductor interfaces and their roles in device thermal management. A highlight will be the use of plasma activated bonding to provide ultralow thermal resistance interfaces that allow for heterogenous integration of nitrides and oxides with high thermal conductivity substrates. Finally, we will discuss the implications of these effects on device behavior through experiments and modeling.

Dielectric polymers play a vital role in modern electronic and electrical application because of easy processing, light weight, and high breakdown strength. A high dielectric constant (εr) and breakdown strength cannot be satisfied simultaneously in the dielectric homopolymers. Via combining the merits of different polymers, the dielectric polymer blending method is a feasible option to address this issue. In this paper, n-type semiconductive polymer poly(1,6,7,12-tetra-chlorinated perylene-N-2-aminoethyl acrylate-N′-dodecylamine-3,4,9,10-tetracarboxylic bisimide) (PPDI) and relaxor ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene) (PVTC) were utilized to prepare the dielectric polymer blends because PPDI had the characteristic of binding electrons and PVTC possessed a high εr. A series of polymer blends with different weight ratios of PPDI were fabricated to investigate the loading effect of an n-type semiconductive polymer on the dielectric and energy storage properties of PPDI/PVTC blends. The experimental results showed that, when the loading was below 3 wt %, the εr of polymer blends increased from 25 to 33 at 102 Hz with the increasing content of polymer PPDI and then decreased from 33 to 7 with the increasing concentration from 3 to 40 wt %. The dielectric behavior of polymer blends was related to the dispersion of organic fillers and interface polarization. Additionally, a low dielectric loss was found in all polymer blending films. A maximal discharge energy density of 4.42 J/cm–3 was achieved in the 4.5 wt % PPDI/PVTC blending film at 200 kV/mm–1. The finding presents an innovative idea to synthesize high-performance all-organic dielectric materials.

As advanced packaging continues to drive towards heterogeneous integration, new materials need to be developed to address the many challenges faced in the assembly process. This presentation will focus on innovative materials for advanced packaging, particularly for small form factor modules, including novel flux formulations for flip chip attach that are compatible with underfill and molding compound, an adhesive agent for fluxless soldering with a formic acid atmosphere, solders with various temperatures for hierarchical soldering. The technology drives toward increased functionality, better efficiency, and higher power density; advanced packaging silicon chip/die size is now bigger, with densely packed interconnect, tighter pitch, and smaller bumps. Some of the common issues we observed due to these are warpage-induced open joints from the big and thin die, flux residue removal challenges due to the tight spacings, and thermal-induced reliability issues. Novel flux formulations and adhesive agents for wafer/die bonding are needed, and interactions between the flux material and various dielectric materials on the wafer need to be better studied. The shift towards using semiconductor-grade ultra-low residue no-clean flip-chip fluxes, which eliminates the cleaning process, is one of the solutions for overcoming these challenges. Another possible solution, studied in recent years, is using a near-zero residue fluxless adhesive agent to hold the die in place while reflowing in a formic acid reflow atmosphere. The development of new solders is also a critical enabler for heterogeneous integration. If there are different reflow cycles that require a solder hierarchy, alloys with varying melting temperatures may be needed for SIP. In addition, lower melting-temperature solders can provide better warpage control, especially for thin die and substrate, as well as for heat-sensitive sensors, die, or substrate that require low-temperature processing. Alloys with enhanced reliability are also needed for certain SIP modules. In summary, proper selection and application of interconnect materials for various assembly processes is crucial to ensuring high production yield for the assembly process of advanced packaging and SIP application.