High density hexagonal MTJ array with 72 nm pitch and 30 nm CD by using advanced DRAM patterning solution and ion beam etch

Perpendicular spin-transfer-torque magnetic random access memory (p-STT-MRAM) is a promising candidate memory device for replacing dynamic random access memory (DRAM) facing with 10-nm sub scaling down. In addition to scaling down, p-STT MRAM has many advantages like fast write/read speed (~10ns) as DRAM, low power consumption (<1pJ), high endurance (>1014), and non-volatility (retention time > 10 years). But to replace DRAM, there are several challenges to be solved. First, high tunneling magneto-resistance (TMR) ratio for read sensing margin. Second, low critical current density(J C) for low power consumption. Third, thermal stability(Δ) for long retention time to save data. And also these parameters should be achieved at 350oC annealing temperature of the back-end-of line (BEOL) to be commercialized. Among them, thermal stability is closely related with cell size. As a cell size of MTJ decreases to achieve a high density memory device, thermal stability decreases with retention time, thus it is not easy to implement both high density and non-volatile memory device simultaneously by decreasing the cell size of MTJ. In our study to solve this issue, we propose the p-STT multi-level cell (MLC) magnetic tunnel junction (MTJ) because MLC MTJ can satisfy both high density and non-volatile memory device at the same time. In particular, we design the MTJ structure with dual free layers and MgO tunnel barriers, so that the MTJ can demonstrate four resistance states. In addition, we investigated the effect of the thickness of two free layers and MgO tunnel barriers on two magneto-resistance (MR) and switching voltage. In our experiments, the p-STT MTJ spin-valves were fabricated on 12-inch-diameter Si/ SiO2/W/TiN wafers by utilizing a 12-in. multi-chamber-cluster magnetron-sputtering system under a high vacuum (less than 110-8 Torr) without breaking the vacuum. Then, all samples were subject to ex-situ annealing at 350℃ at a back end of line (BEOL) for 30 minutes under a magnetic field of 3 tesla. In our presentation, we present how to optimize the thicknesses of two free layers and MgO tunnel barriers. In addition, we repot how the magnetic behavior and the resistance of MTJ is affected by magnetic and how the magneto-resistance of MTJ is closely related to the crystallinity of two MgO tunnel barriers. Acknowledgements This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2017R1A2A1A05001285)

Patterning damage at the sidewall in a magnetic tunnel junction (MTJ) was observed precisely using a rectangular MTJ where deterioration in crystallinity is easier to identify than in the case of a dot-shaped conventional MTJ. A 200–500 nm-square rectangular MTJ was patterned by a 200 eV ion beam (IB). Cross-sectional transmission electron microscopy was used for damage observation. A bright-field image showed that crystallinity deteriorated to a depth of $\sim 1.3$ nm in the MgO-barrier layer. A Fourier transform mapping image and a dark-field transmission electron microscopy image indicated the existence of an amorphous region at the patterning edge in the MgO layer. IB etching is one of the strong candidates for magnetic random access memory (MRAM) fabrication. However, a typical IB etching energy, e.g., 200 eV, introduces a damage depth of several monolayers at the patterned surface. Since nearly damage-free-patterned surface would be needed for high-density MRAM with nanoscale MTJs of $\sim 10$ nm in diameter, IB etching with much lower energy would be necessary for fabrication.

The authors have demonstrated fabrication of 30 nm diameter perpendicular anisotropy magnetic tunnel junctions (MTJs) using negative electron-beam resist (NER) as the ion beam etching (IBE) hard mask. The NER pillar of 30 nm diameter and 105 nm thickness was fabricated by electron-beam lithography. The redeposition of the MTJ etching debris generated during the IBE on the outer surface of the NER pillar increased the lateral etch resistance of the resist polymer, allowing the edge profile to remain constant for the duration of the MTJ etching, resulting in a vertical MTJ sidewall profile. A multistep IBE (repetition of 45° primary etching and 30° secondary etching) was conducted to reduce the MTJ sidewall redeposition while reducing mechanical damage. The measurement results showed a tunnel magneto-resistance ratio of 22% at 30 nm junction diameter.

Background: With continuous decrease in the technology node of dynamic random access memories (DRAMs) down to sub-20 nm, the self-aligned double patterning (SADP) is an effective approach to generate two-dimensional (2-D) patterns, particularly contact arrays. Aim: We demonstrate a patterning scheme using the SADP technique to produce active trim contacts with anisotropic pattern pitches. Approach: The proposed scheme uses two consecutive spacer-formation processes. Results: By making the ellipsoidal core pillars and minimizing the spacer thickness, 2-D critical dimensions (CDs) for self-generated contacts match well with those for core contacts. In addition, an interesting cross-dependence of X -CD and Y -CD variations for the core and self-generated contacts is observed. Conclusion: This patterning approach is useful for forming active trim contacts in sub-20 nm DRAMs using fewer numbers of ArF immersion photolithography steps.

ABSTRACTSurface smoothing of Ru used as underlayer of magnetic tunneling junctions (MTJ) in magneto-resistive random access memory (MRAM) was carried out with gas cluster ion beam (GCIB) in order to improve device characteristics. For Ru films, surface smoothing with 5 kV N2-GCIB irradiation was effective, and CoFe films deposited on smoothed Ru surface also showed smooth surface. From the hysteresis loop measurements of MTJ formed on smoothed Ru with N2-GCIB, it showed improvement of inter-layer coupling magnetic field (Hin) with decreasing the surface roughness of underlayer Ru. It is expected that surface roughness of MgO in MTJ was also improved by smoothing of underlayer Ru with N2-GCIB.

As the memory market becomes more diverse, the conventional memory hierarchies composed of Flash memory, DRAM and SRAM are now being asked to have various and segmented system to fill the gap between the current memory systems in terms of the cost and performance. The nonvolatile memory will upgrade the current memory subsystems and enable the stable system architectures that retain their state even when power is off. The emerging memories will not directly replace the existing memory (DRAM and Flash memory) but will make a new memory class. The attributes of STT-MRAM can lead to adopt in-memory computing architectures for the embedded memory solution SoC. In these circumstances, the accurate and scalable model of magnetic tunnel junction (MTJ) is required to accelerate the commercialization of STT-MRAM. In this thesis, after the MTJ basics is introduced as a storage element and the magnetic dynamics to utilize the electron spins as wells as the electron charges, the parallel and anti-parallel magnetization configuration is explained in terms of the band structure to understand the basic operation of the MTJ in memory cell. To demonstrate the viability of MTJ as a memory cell, the switching mechanism, reading/writing scheme, and some important parameters in STT-MRAMs such as TMR (Tunneling Magnetoresistance), Switching current (Ic), and Thermal Stability (Δ) are investigated. As a test vehicle of the technology, a set of RAM is designed in this research to show its efficiency and advantages of MTJ memory cell. As a first step of the design, the scalable model of a MTJ that accurately depicts the spin-transfer torque dynamic switching behavior of a MTJ is verified along with its bias voltage and Temperature dependency. The model integrates the physical models of static and dynamic behaviors; many experimental parameters are provided to see the process variations, especially temperature and bias voltage perspective. Based on the verified model, a set of RAM circuit is designed, and the designed STT-MRAM circuit's behavior and performances are analyzed to find the optimum tunnel magnetoresistance (TMR) ratio and switching performance. Of the compact model of the CoFeB/MgO PMA-MTJ (perpendicular magnetic anisotropy MTJ). The whole circuit was designed in a standard 45nm CMOS technology using MTJ. The measurement shows that the switching delay of MTJ increases by 5.5ns with growing tunnel barrier oxide (MgO) thickness from 0.85nm to 1.15nm. A bit longer delay for writing is observed as expected. The simulation shows a trade-off between memory access time and MTJ area as the switching delay of MTJ decreases by 6.5ns when the MTJ area increases from 1010nm to 4040nm. For reading operation of the memory, the conventional sense amplifier circuit is employed to detect the stored bit-cell. In the reading peripheral circuits including sense amplifier, the fixed reference voltage (0.9V) is used to simplify the analysis. The reading operation and peripheral block of memory circuits is verified successfully with read access time of 1.47ns.--Author's abstract

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

This report investigates the current-induced switching of exchange bias without an external magnetic field in nano-scaled magnetic tunnel junction (MTJ) cells. An MTJ stack film was patterned into an ellipse with dimensions of 120 nm × 270 nm by using standard electron beam lithography in combination with ion beam etching. A spin-polarized current pulse with a duration of 100 ns was used to switch the exchange bias direction of the synthetic antiferromagnetic (SAF) pinned layer. It is worth noting that the MTJ cell was initialized in a high resistance state before applying the current pulse. For the application of both positive and negative current pulses, the resistance can be switched from the high (antiparallel) state to the low (parallel) one at 2.95 and −2.80 mA, respectively. After the current-induced switching, it was found that the magnetoresistance curve is reversed relative to the one before the current-induced switching. Predominantly, this behavior is independent of the polarity of the current pulse. As a result, it is shown that the exchange bias in the SAF pinned layer changes its direction with a sufficient supply of current pulse.

Two-dimensional (2D) materials embedded in magnetic tunnel junctions (MTJs) provide a platform to increase the control over spin transport properties by the proximity spin-filtering effect. This could be harnessed to craft spintronic devices with low power consumption and high performance. We explore the spin transport in the 2D MTJs based on graphene, which is uniformly grown on Ni(111) substrates using the chemical vapor deposition technique. After the Ni thin film is deposited bottom-up on the well-grown Ni(111)/graphene surface in an e-beam evaporation system by the physical vapor deposition method, the Ni/graphene/Ni nanojunction array devices are successfully prepared by using nanography technology. Evidence of the emergence of tunneling magnetoresistance (TMR) effects with ultrasmall resistance × area products in graphene-based nanojunctions is observed by the exclusion of anisotropic magnetoresistance. The theoretical analysis shows that this TMR is mainly attributed to the strong spin-filtering effect at the perfect Ni(111)/graphene interface. Besides, earlier findings indicate that the TMR would be promoted more effectively if the short-circuit effect formed in the process of nanographic etching by an ion beam can be further eliminated. Overall, this study provides a path to harness the full potential of graphene-based MTJ array devices with a high efficiency and performance.

Dynamic random access memory (DRAM) is one key component in modern electronic systems. In this paper, we propose a software-hardware-cooperated built-in self-test (SHC-BIST) scheme for the channel-based DRAMs. The testing of DRAMs consists of two major phases: DRAM initialization and DRAM array testing. Typically, the DRAM initialization process is short and executed in the beginning of the DRAM array testing. Thus, it is inefficient to realize it using the dedicated BIST hardware. On the other hand, it is not time efficient if we use the processor (software) to execute the DRAM array testing. Therefore, the SHC-BIST scheme uses a programmable BIST circuit to execute the DRAM array testing and takes advantage of the processor to execute the DRAM initialization and control the programmable BIST circuit such that the test time and hardware cost can be minimized. We verify the SHC-BIST scheme using a system with a LEON3 processor and a multi-channel DRAM.

The discovery of giant magnetoresistance (GMR) in magnetic multilayers (Baibich et al., 1988) and of tunnel magnetoresistance (TMR) in metal/insulator junctions (Julliere, 1975) has marked the beginning of spin electronics, which makes use of the electron’s spin as an additional degree of freedom, thus enabling novel phenomena and devices to be imagined. The GMR spin valves (Dieny et al., 1991; Parkin, 1993) have already been integrated in many functional devices like magnetic read heads, angle and position sensors and low-capacity random access memories (RAM). The TMR tunnel junctions are mainly proposed for non-volatile magnetic memories (MRAM) which combine all the advantages of conventional memories such as DRAM (dynamic RAM), SRAM (static RAM) or flash: short access time, non-volatility, insensibility to ionizing radiation, high density, infinite cyclabilty. Major IC manufacturers are now ready to launch the first fully functional prototypes.

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding “1”. The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading “1” to reading “0” (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

In this paper, the dynamic random access memory (DRAM) cell technology is introduced and the important technological breakthroughs are reviewed. The criteria of DRAM memory cell design is discussed and the key fabrication technologies of 6F2 memory cell and stack capacitor DRAM cell are summarized. The technological evolution of array access transistor is also reviewed. The transistors with U-shaped transistor or FinFET and the fabrication process flow of 6F2 DRAM chip were discussed. Based upon the technical requirements for DRAM cell, the possible device technologies for the next generation DRAM cell was summarized. It is predicted that (1) U-shape channel transistor will be the mainstream technology for the future DRAM cell beyond 20 nm; (2) low k material will be required for decreasing the bitline parasitic capacitance; (3) sense-amplifier with better signal-noise margin will be required to ease the requirement of high aspect-ratio storage capacitance; (4) low power DRAM design will draw more attention, rather than increasing the storage capacity of DRAM.

Journaling techniques play an important role in addressing the reliability issue of filesystems caused by the volatile dynamic random access memory (DRAM)-based buffer cache. However, journaling techniques introduce a large number of extra storage writes, which greatly degrades system performance, especially for mobile devices. Emerging nonvolatile memory (NVM) technologies bring a new perspective of solving the write amplification issue caused by journaling. By adopting NVM as the buffer cache, the committed data can be maintained in NVM before being written back to the storage, thus, eliminating the journaling overhead. However, simply utilizing NVM as the buffer cache suffers from the limited lifetime and the relatively longer write latency of NVM. In this paper, we present a hybrid buffer cache architecture, named UniBuffer, by combing NVM with dynamic random access memory (DRAM) to reduce the journaling overhead and overcome the inherent constraints of NVM. In UniBuffer, we first propose a journaling-aware page management (JAPM) policy to smartly allocate data to DRAM and NVM pages. JAPM puts infrequently updated data in NVM to reduce the journaling overhead and frequently updated data in DRAM to improve the write performance and lifetime of the hybrid buffer cache. In addition, since data in one journaling transaction may be dispersed in NVM and DRAM simultaneously, different committing policies are required for different storage media, respectively. In order to guarantee the atomicity of the transaction execution in the hybrid cache architecture, a partial in-place commit (PIPC) journaling scheme is proposed to coordinate different committing patterns for NVM and DRAM. We have implemented the proposed techniques on Linux 3.14.52 and measured the performance with representative I/O-intensive benchmarks. The experimental results show that our scheme effectively improves the I/O performance compared with the ext4 filesystem and prolongs the lifetime of the hybrid buffer cache compared with the union of buffer cache and journaling (UBJ) scheme.

Dynamic random access memory (DRAM) is facing the challenge of technology scaling. The de-creasing feature size makes it harder to make DRAM cells which can keep the current data-holding time. When DRAM cells cannot hold data for a long time, DRAM chips need a more frequent refreshing operation. There-fore, in the near future, time and energy cost on DRAM refreshing will be no longer trivial. In this paper, we propose DRAM Error Correction Pointer (ECP), an error-correction-manner framework, to reduce DRAM re-freshes without data loss. We exploit the non-uniform feature of DRAM cells with respect to the data retention time. Compared with the conventional refreshing mechanisms, which refresh DRAM chips by the retention time of the leakiest cells, we refresh the chips much fewer times, and treat the not-in-time refreshed cells as fault elements. We use the structure of ECP as a fault tolerant element. By recording the data which are supposed to be written into the leaky cells in our DRAM-ECP structures, DRAM-ECP can significantly decrease refreshing frequency. When these data are to be read out, DRAM-ECP retrieves the data stored in ECPs and covers them to the corresponding position in the data row. Our experiments show that DRAM-ECP can reduce over 70% refreshing operations than the current refreshing mechanism and also get significant energy saving.