High-Gain Non-isolated Single-Switch DC-DC Converters in Power Factor Correction Rectifiers: A Performance Assessment

In the first part of this paper, three-phase power factor correction (PFC) rectifier topologies with sinusoidal input currents and controlled output voltage are derived from known single-phase PFC rectifier systems and/or passive three-phase diode rectifiers. The systems are classified into hybrid and fully active pulsewidth modulation boost-type or buck-type rectifiers, and their functionality and basic control concepts are briefly described. This facilitates the understanding of the operating principle of three-phase PFC rectifiers starting from single-phase systems, and organizes and completes the knowledge base with a new hybrid three-phase buck-type PFC rectifier topology denominated as Swiss Rectifier. Finally, core topics of future research on three-phase PFC rectifier systems are discussed, such as the analysis of novel hybrid buck-type PFC rectifier topologies, the direct input current control of buck-type systems, and the multi-objective optimization of PFC rectifier systems. The second part of this paper is dedicated to a comparative evaluation of four rectifier systems offering a high potential for industrial applications based on simple and demonstrative performance metrics concerning the semiconductor stresses, the loading and volume of the main passive components, the differential mode and common mode electromagnetic interference noise level, and ultimately the achievable converter efficiency and power density. The results are substantiated with selected examples of hardware prototypes that are optimized for efficiency and/or power density.

ISSN:2168-6777

A three-phase ac/dc converter with high-frequency isolation can be realized as a monolithic three-phase or as a phase-modular system by combining three single-phase Power Factor Correction (PFC) rectifier modules with individual isolated dc-dc converters. Advantageously, for a phase-modular system the module configuration can be changed depending on the instantaneous input-output voltage ratio (i.e., a star-(Y)- or a delta-(Δ)-arrangement such that wide voltage ranges can be covered without a massive over-dimensioning of the main power components. However, the main disadvantage of a phase-modular converter realization is the fact that the input power of each PFC rectifier module pulsates at twice the mains frequency (which is inherent to single-phase power conversion) such that large dc-link capacitors are required. Recent literature predicts a substantial power pulsation reduction enabled by means of third-(3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> )-harmonic injection modulation which is applicable for the Y-connection (where a common-mode (CM) / zero-sequence (ZS) voltage is injected), and for the Δ-connection of the three single-phase PFC rectifier modules (where a CM / ZS current is injected). This changes the distribution of the power flow in the three-phase system and the power pulsation is shifted to higher frequencies. This paper experimentally verifies and extends the dc-link energy storage requirement reduction of the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation concept: In a first step, the derivation of the harmonic injection concept is recapitulated and suitable control methods are discussed for both CM voltage (Y-arrangement) and CM current (Δ-arrangement) injection. Further, an alternative CM voltage injection strategy with simplified reference generation based only on the instantaneous grid voltage measurements is presented and compared to the pure 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation. Measurement results obtained from a 6 kW prototype reveal a dc-link voltage variation and/or energy buffering reduction by up to 38.6 % enabled by the harmonic injection modulation compared to conventional operation without 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -harmonic injection modulation.

This paper describes a digital controller for high-frequency single-phase power factor correction rectifiers (PFC) that is suitable for on-chip implementation. To achieve high switching frequency, fast dynamic response, and implementation with a small number of logic gates, the designs of basic functional blocks are optimized. In the outer voltage loop a windowed based analog-to-digital converter (ADC) with adjustable quantization steps is used, to achieve fast dynamic response. The complexity of the current loop realization is significantly reduced through the utilization of a floating reference created by a Sigma-Delta modulator and another windowed based ADC. In addition, a segmented ring-oscillator based digital pulse-width modulator (DPWM) is used to eliminate the need for a high frequency external clock and reduce the overall size of the system. The effectiveness of this digital architecture is demonstrated on a 200 kHz, 300 W boost-based PFC experimental prototype.

This paper presents a Scott transformer based three-phase, two-switch PFC (Power Factor Correction) boost rectifier for improving the power quality in a three-level diode clamped inverter (DCI) feeding indirect rotor field oriented control (FOC) based induction motor drive (IMD). Sinusoidal unity power factor source current and dc-link voltage regulation are achieved in the proposed rectifier only with two-switches. The three-level DCI is supplied by a split dc-link obtained from a Scott connected transformer feeding a rectifier. It is shown that a three-level DCI achieves reduced stator current with lower voltage harmonic content even at a lower switching frequency as compared to a two-level inverter. This results in reduction of voltage stress on motor windings for the same amount of torque ripple when indirect rotor FOC algorithm is implemented for the IMD. A MATLAB based simulation model of proposed PFC rectifier is developed for validating the design and to verify that the power quality issues in three-level DCI fed IMD are adequately addressed. The performance of the system is studied and compared with a conventional diode rectifier fed vector controlled IMD for different operating conditions of the drive.

This paper introduces a novel algorithm for implementing the digital control method for the single power factor correction (PFC) rectifier. The switching frequency of power semiconductor is variable under different load conditions. The duty cycle is calculated based on digital non-linear control (DNLC) method without the input voltage-sensing circuit. Simulation results of a boost power PFC prototype point out that high power factor and low input current total harmonic distortion (THD) are achieved using proposed control strategy.

This paper presents one dynamic regulation of controller parameters strategy for power factor correction (PFC) rectifier, which is based three-phase Vienna topology. To improve the converter power-density, the operation with high frequency and fast calculation is required. In this paper, the proposed controller is based on digitized feedforward compensation approach, can improve the control system dynamic response and simplify the algorithm. In addition, by adjusting the error coefficient of positive and negative dc-link ensures quickly maintaining the neutral point voltage balance under lightly or no load conditions. The theoretical analysis of the proposed strategy is deduced, and, the controller parameters design method is given. Finally, the simulation and experimental results are obtained by using a digitally controlled Vienna rectifier, which validates the proposed method.

In this paper, MOSFET gate drive signals are omitted in critical conduction mode (CRM) boost power factor correction (PFC) rectifier to reduce the power consumption of the controller circuit and improve the light load efficiency. Because the gate signals are selectively omitted when the rectifier carries neither average input current nor output diode current, the effect of gate signal omission has the minimal effect on input current distortion and output voltage regulation. The feasibility of the gate signal omission technique is verified by the experiments conducted with prototype hardware. © 2012 IEEE.

This paper proposes a novel non-isolated high gain dc-dc (NHGDC) converter using a switched inductor-capacitor network. The converter has twelve components including the four capacitors, two inductors, five diodes and one semiconductor switch. Though the NHGDC converter has twelve components, it uses only one semiconductor switch and achieves a maximum theoretical gain of twenty at a duty ratio of 0.8. The steady-state output voltage equation of the converter is derived with the help of the analytical waveforms. The theoretical voltage gain of the NHGDC converter is 4/(1-d). Thus, the NHGDC converter is named as a double2 gain converter. The voltage gain of the high gain dc-dc converters is significantly affected due to the parasitic elements of various components present in the converter. So, a detailed analysis has been conducted to assess the effect of parasitic elements on the output voltage of the double2 gain converter. The proposed structure has only passive elements in the discharging path when the energy is discharged into the load side. The performance comparison has been conducted to measure the potential merits of the double2 gain converter compared to the recently reported high gain dc-dc converters. A hardware prototype of the double2 gain converter has been fabricated, and an experimental setup is assembled in the laboratory for testing. The output waveforms from various parts of the converter are observed during the testing, and the waveforms are presented in this paper. The double2 gain converter will be useful for the integration of the low voltage dc sources such as ultracapacitor, fuel cell, battery, etc.

Multilevel converters are recent alternative ways of implementing high power medium voltage applications compared with two-level converters. This paper presents a three-level pulse-width modulation scheme based on the diode clamped rectifier for power factor correction. Eight power switches are employed in the adopted switching mode rectifier. The voltage stress of each power switch is only half of the dc-link voltage. This advantage allows the low voltage stress semiconductor to be used in the high voltage applications. The control scheme is based on a look-up table to achieve high power factor and low current harmonics to meet the harmonic limits of International Electrotechnical Commission standard 1000-3-2. The neutral point voltage balance problem is overcome by using a voltage compensator to reduce the voltage variation under the unbalanced load condition. The proposed control technique illustrates its validity and effectiveness through simulations and experiments.

Single-phase rectifier systems often require simultaneously high power factor, efficiency, and power density but can be difficult to implement with conventional solutions. In this work, a 1.5 kW, universal (95 to 265 $\mathbf{V}_{rms}$ ) ac input, 400 V dc output power factor correction (PFC) rectifier with a flying capacitor multilevel (FCML) boost front-end and a series-stacked buffer (SSB) for twice-line frequency energy buffering is implemented to meet these stringent high performance design requirements. Specifically, a PLL-based SSB control method is proposed and characterized for system integration with a generalized PFC front-end. The impacts of the SSB on the PFC front-end performance as well as the impacts of the PFC front-end behavior on SSB performance are analyzed and discussed. The interdependence of this SSB control and the PFC control architecture are validated through appropriate system modeling and experimental verification.

The paper presents an efficient speed control of brushless DC (BLDC) motor drive for photo-voltaic (PV) system fed system. A high-gain DC-DC converter is employed in the system to boost the PV system low output voltage to a level required for the drive system. High-gain DC-DC converter is operated in closed-loop mode to attain accurate and steady output. The converter (VSI) for BLDC is switched at fundamental frequency and thus reducing high frequency switching losses. Internal current control method is developed and employed for the speed control of PV fed BLDC motor. The appropriateness of the internal current controller for the speed control of PV fed BLDC motor is verified for increamental speed with fixed torque and decreamental speed with fixed torque operating conditions. The system is developed and results are developed using MATLAB/SIMULINK software

Single-phase ac-dc Power Factor Correction (PFC) rectifiers have attracted considerable attention in recent years due to the adoption of increasingly stringent power quality regulations. In this paper a nonlinear model predictive controller design for a single-phase Flyback PFC rectifier is presented. After approximation of the tracking error in the receding horizon by its Taylor-series expansion to a specified order, an analytic solution to the model predictive control (MPC) is developed and a closed-loop nonlinear predictive controller is introduced. The main advantage of this digital control method is that unity power factor can be achieved over wide input voltage, load current range and on high dynamics directly depend on the processing speed of microprocessor. This method is applied to a flyback PFC rectifier, can improve the voltage control dynamics. Simulation results show that flyback PFC rectifier with NMPC provides better and more accurate performance in both steady states and transient compared to linear control methods.

This study presents a zero‐voltage‐transition (ZVT) bridgeless power factor correction (PFC) rectifier, which uses an auxiliary circuit with a transformer to achieve soft‐switching for the main power switches. With the auxiliary circuit, the main switches can be ZVT turned‐on without any additional voltage or current stresses. In addition, the auxiliary switch is turned‐off with zero‐current switching. Therefore, the switching loss of all power switches is reduced, and the overall rectifier efficiency is improved. The circuit topology, operation analysis and the components selection of the proposed rectifier are described in detail. Finally, a laboratory prototype of 700 W is implemented and tested to verify the performance of the proposed PFC rectifier.

This paper addresses input current distortion issue and proposes mitigation techniques for current distortion in negative coupled inductor based two-channel interleaved critical conduction mode (CRM) totem-pole power factor correction (PFC) rectifier. Due to dynamic equivalent inductance characteristic of the coupled inductor, the input current distortion becomes significant, particularly when the duty cycle approaches 0.5. This distortion consists of high frequency distortion caused by non-perfect interleaving and low frequency distortion resulting from slow response of controller. Proposed feed-forward calculation is introduced to enhance the controller's dynamic response and minimize low frequency distortion. In addition, an adaptive switching frequency operation method is proposed to maintain perfect interleaving, thereby minimizing high-frequency distortion. The proposed methods are verified in the 7kW CRM totem-pole PFC rectifier prototype with negative coupled inductor.