High-level modeling and synthesis for embedded FPGAs

Wireless sensor network (WSN) applications have been studied extensively in recent years. Such applications involve resource-limited embedded sensor nodes that have small size and low power requirements. Based on the need for extended network lifetimes in WSNs in terms of energy use, the energy efficiency of computation and communication operations in the sensor nodes becomes critical. Digital Signal Processing (DSP) applications typically require intensive data processing operations and as a result are difficult to implement directly in resource-limited WSNs. In this article, we present a novel design methodology for modeling and implementing computationally intensive DSP applications applied to wireless sensor networks. This methodology explores efficient modeling techniques for DSP applications, including data sensing and processing; derives formulations of Energy-Driven Partitioning (EDP) for distributing such applications across wireless sensor networks; and develops efficient heuristic algorithms for finding partitioning results that maximize the network lifetime. To address such an energy-driven partitioning problem, this article provides a new way of aggregating data and reducing communication traffic among nodes based on application analysis. By considering low data token delivery points and the distribution of computation in the application, our approach finds energy-efficient trade-offs between data communication and computation.

As computation migrates to the edge, energy efficiency is becoming even more critical in the design of electronic devices. Therefore, new applications for the Internet of Things pose a challenge for designers to find the optimal balance between performance and energy consumption. While Coarse Grained Reconfigurable Architectures (CGRA) have been an alternative to provide the required acceleration, they are far from being the most energy-efficient, since their functional units may be underutilized by some applications. In this work, we introduce a novel approach to handle these CGRA resources, which leverages the variable usage of functional units due to the application program phases. By using our new approach and performing power-gating of under-utilized parts of the CGRA, we demonstrate that it is possible to achieve reductions of up to 52.3% in power dissipation and 75% in energy consumption.

Mobile computing as exemplified by the smart phone has become an integral part of our daily lives. The next generation of these devices will be driven by providing richer user experiences and compelling capabilities: higher definition multimedia, 3D graphics, augmented reality, and voice interfaces. To meet these goals, the core computing capabilities of mobile terminals must be scaled within highly constrained energy budgets. Coarse-grained reconfigurable architectures (CGRAs) are an appealing hardware platform for mobile systems by providing programmability with the potential for high computational throughput, low cost, and energy efficiency. CGRAs are most commonly used for innermost loops that contain an abundance of instruction-level parallelism. Unfortunately, current CGRAs fail to meet future performance requirements due to their inability to scale. Simply increasing the size of the array is too expensive in terms of power and area. In this paper, we first perform a deep analysis of several mobile applications from the domains of multimedia and gaming. We then explore potential solutions in the context of these applications for scaling the array performance in an energy efficient manner: homogeneous versus heterogeneous functionality, interconnect topologies, simple versus complex processing elements, and scalar versus vector memory support.

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing the potential for high computation throughput, scalability, low cost, and energy efficiency. CGRAs consist of an array of function units and register files often organized as a two dimensional grid. The most difficult challenge in deploying CGRAs is compiler scheduling technology that can efficiently map software implementations of compute intensive loops onto the array. Traditional schedulers focus on the placement of operations in time and space. With CGRAs, the challenge of placement is compounded by the need to explicitly route operands from producers to consumers. To systematically attack this problem, we take an edge-centric approach to modulo scheduling that focuses on the routing problem as its primary objective. With edge-centric modulo scheduling (EMS), placement is a by-product of the routing process, and the schedule is developed by routing each edge in the dataflow graph. Routing cost metrics provide the scheduler with a global perspective to guide selection. Experiments on a wide variety of compute-intensive loops from the multimedia domain show that EMS improves throughput by 25% over traditional iterative modulo scheduling, and achieves 98% of the throughput of simulated annealing techniques at a fraction of the compilation time.

This paper presents a method to time share the Processing Elements (PEs) of Runtime Coarse Grain Reconfigurable Architectures (CGRA) among multiple processes being executed concurrently onto the same CGRA. Runtime CGRA architectures time-multiplex the data path, creating a set of contexts for each state. These contexts configure the PEs and the routing resources of the CGRA and are typically loaded every clock cycle. The target architecture in this work is a commercial CGRA IP which is embedded as an IP into complex SoCs. Our proposed method analyzes the PE utilization in each context for multi-process systems running concurrently onto the same CGRA and time shares unused PEs assigned to one process with the other processes running in parallel. Our method reduces the total PE usage and hence the size of the CGRA IP and therefore the cost of the SoC. Results show that our method is extremely efficient and can reduce the PE utilization by up to 20% and on average by 14% and is only 2% worse than the optimal solution, while being much faster.

Coarse-grained reconfigurable architectures (CGRAs) are increasingly employed as domain-specific accelerators due to their efficiency and flexibility. A CGRA typically relies on compilers to perform task scheduling. The longstanding problem of static scheduling is that it suffers from insufficient parallelism in handling irregularities due to over-serialization and workload imbalance, which leads to severe resource underutilization and performance loss. To counteract the limitations of static scheduling in CGRAs, it is essential to exploit dynamic parallelism automatically and manage hardware resources adaptively. However, existing dynamic scheduling mechanisms, e.g., work stealing, often reschedule aggressively for instant performance but sacrifice efficiency, which is unfavorable to CGRAs that emphasize efficiency and fewer reconfigurations. This article proposes an elastic task scheduling scheme that enables lightweight dynamic scheduling in CGRAs. Tasks are rescheduled at runtime according to the classic tagged-token dataflow paradigm to enable dynamic task-level parallelism. Meanwhile, tasks are dynamically resized according to run-time throughputs via duplication, combination, and substitution operators for balanced multitask execution. We implement the elastic task scheduling scheme on a well-known reconfigurable architecture - triggered instruction architecture (TIA). Evaluation on the MachSuite benchmarks shows that the proposed scheme is effective in improving performance and energy efficiency. The average speedup is 2× over the baseline. Also, our design attains a 57 percent improvement in the area-normalized performance and a 49 percent better energy efficiency. Compared with a state-of-the-art dynamic scheduling method, our scheme achieves 1.6× speedup and 1.6× energy efficiency than work-stealing mechanism on the same substrate.

Emerging communication technologies, such as 5G and beyond, have introduced diverse requirements that demand high performance and energy efficiency at all levels. Furthermore, the real-time requirements of different services vary significantly — increasing the baseband processor design complexity and demand for flexible hardware platforms. This paper identifies the key characteristics of hardware platforms for baseband processing and describes the existing processing limitations in traditional architectures. In this paper, Coarse-Grained Reconfigurable Architecture (CGRA) is examined as a prospective hardware platform and its characteristic features are highlighted as compared to traditionally employed architectures that make it a suitable candidate for incorporation as a domain-specific accelerator in baseband processing applications. We survey various CGRAs from the last two decades (2004-2023) and analyze their distinct architectural features which can serve as a reference while designing CGRAs for baseband processing applications. Moreover, we investigate the existing challenges toward developing CGRAs for baseband processing and explore their potential solutions. We also provide an overview of the emerging research directions for CGRA and how they can contribute toward the development of advanced baseband processors. Lastly, we highlight a conceptual RISC-V+CGRA framework that can serve as a potential direction toward integrating CGRA in future baseband processing systems.

The article highlights the latest developments in the design of low-power 4-bit Absolute Value Detector (AVD) circuits that are utilized in digital signal processing (DSP) applications. DSP applications like audio and video processing, biological signal processing, and digital communication systems rely heavily on the AVD circuit, which determines the absolute value of an input signal. The article introduces a low-energy 4-bit AVD circuit based on pass transistors that incorporates advanced optimization techniques like adiabatic logic, approximation techniques, and layout optimization. This optimized AVD circuit achieves remarkable results in terms of power consumption and energy efficiency. With a power consumption of just 0.6 nW and an energy efficiency of 0.6 pJ per cycle, the circuit maintains precision and rapid response time. These advancements in AVD circuit design can be highly beneficial for portable and battery-powered devices such as earplugs, implants, and cell phones, as well as electronic components like Static Random Access Memory (SRAM) and motherboards. Overall, the proposed low-energy 4-bit AVD circuit is a significant development in the DSP field, enabling more efficient and effective processing of digital signals.

Finite Impulse Response (FIR) Filter occupied a significant position in most of Digital Signal Processing (DSP) Applications. The behaviour of FIR filters can be realized in software for DSP applications and executed on Digital Signal Processor architectures. These kinds of digital filters consider digital components, digital input and perform mathematical computations to produce digital output. In modern DSP applications demanding area efficient architecture for DSP algorithms while optimizing throughput. This can be achieved by design of hardware architectures for DSP algorithms and apply design optimization techniques to accelerate the throughput and minimize area. This article attempts to develop hardware architectures for FIR Filter and apply the design optimization techniques present in literature. In this article, High Level Synthesis concepts were adapted to develop hardware architecture for FIR filter and optimization techniques have been applied to optimize design attributes like area, throughput and power. Finally, design attributes are summarized after applying optimization techniques and published significant architectural attributes suitable for real life DSP applications.

Coarse-grained reconfigurable architectures (CGRAs) are gaining increasing attention as domain-specific accelerators due to their high flexibility and energy efficiency. These architectures offer a compelling solution for applications that require custom hardware performance while retaining a degree of programmability. However, the design space of CGRAs is inherently vast and complex, presenting significant challenges for architects to explore design choices efficiently and systematically. Existing design space exploration (DSE) methodologies for CGRAs are often time-demanding and struggle to deliver optimal solutions when confronted with high-dimensional and multi-objective design space. Therefore, we consider constructing a CGRA parameter tuning framework called MoDAF. MoDAF initializes the design space using the most representative and diverse samples. It adopts a divide-and-conquer approach, utilizing Monte Carlo Tree Search (MCTS) and space partitioning techniques to dynamically break down the complex design space into more manageable subspaces. A hybrid model handles local fluctuations within each subspace, while a dual sampling algorithm is designed to increase sampling efficiency. MoDAF also incorporates a fast evaluation model to estimate CGRA throughput and area, significantly speeding up the exploration process. Compared with previous approaches, experiments show that our proposed framework reduces the average distance from the reference set by 53.0% and the hypervolume deviation by 64.2%, while also cutting wall time by 57.5%.

Energy efficient configuration unification and compression for CGRAs

Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. Reversibility plays an important role when energy efficient computations are considered. Reversible logic is used to reduce the power dissipation that occurs in classical circuits by preventing the loss of information. This paper proposes a reversible design of a 16 bit ALU. This ALU consists of eight operations, three arithmetic and five logical operations. The arithmetic operations include addition, subtraction, multiplication and the logical operations include NAND, AND, OR, NOT and XOR. All the modules are being designed using the basic reversible gates. The power and delay analysis of the various sub modules is performed and a comparison with the traditional circuits is also carried out.

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

Coarse-Grained Reconfigurable Architectures (CGRAs), which provide good trade-offs between performance, hardware/ energy efficiency and flexibility, as well as offer high degree of parallelism, are fast emerging as a competing platform for the high-performance and embedded applications [3]. In this paper, we propose a timing driven approach for generating cycle-accurate high level simulator for CGRA. The simulator is generated from a high-level language describing the CGRA. Experimental results on different architectures and application kernels show that the proposed simulator is \(1.5\times \) to \(4\times \) faster than state-of-the-art RTL simulators.