High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor

Reconfigurable Computing (RC) is a promising paradigm that addresses the conflicting hardware design requirements of high performance and area efficiency. Coarsegrained architecture RC (CGA-RC) operates at the word level of granularity and exhibits better power and performance than fine-grained architectures. High level synthesis for Coarse-Grained Architecture Reconfigurable Computing (CGA-RC) devices from high-level descriptions is urgently needed to improve design efficiency. To realize this, it is also necessary to achieve both good performance and high PE (Processing Element) utilization automatically for all applications. In this paper, we address this issue by focusing on nested loop pipelining and hierarchical allocation of PEs and propose an algorithm to generate CGA-RC circuit configurations automatically. The methodology is compared with other methods to evaluate its performance.

Due to the intrinsic difference between fan-in and fan-out counts of a retimed component, the number of flip-flops tends to be undesirably increased in a conventional retiming procedure, which can cause a significant area/power penalty on the retimed circuit. Nonetheless, because of the higher dominance on interconnect delays, without a mechanism to reflect real physical design accurately, the clock period produced by a retiming scheme will be unrealistic. To overcome these two major drawbacks of the conventional retiming technique, we propose a novel retiming flow combined with rewiring, being able to largely cut down flip-flops (FFs) while with the original retimed clock period uncompromised. For a more accurate delay estimation, all interconnect delays are formulated and calculated based on real placements. Experimental results show that this novel rewired retiming scheme can bring a reduction of 18.7% (on average) on the number of flip-flops compared to the original retiming without rewiring. This large FF reduction can be considered a free gain as the retimed clock period can still be kept without compromise in such flow. Further experiments have indicated that about 8.26% of the total dynamic power can be saved.

As well as the schedule affects system performance, the control skew, i.e., the arrival time difference of control signals between registers, can be utilized for improving the system performance, enhancing robustness against delay variations, etc. The simultaneous optimization of the control step assignment and the control skew assignment is more powerful technique in improving performance. In this paper, firstly, we prove that, even if the execution sequence of operations which are assigned to the same resource is fixed, the simultaneous optimization problem under a fixed clock period is NP-hard. Secondly, we propose a heuristic algorithm for the simultaneous control step and skew optimization under given clock period, and we show how much the simultaneous optimization improves system performance. This paper is the first one that uses the intentional skew to shorten control steps under a specified clock period. The proposed algorithm has the potential to play a central role in various scenarios of skew-aware high level synthesis.

3D NOC for many-core processors

Computer architectures are expected to change to support Exascale computing in the near future. As energy and cooling constraints limit increases in microprocessor clock speeds and number of cores, computer companies are turning to parallel programming. Nowadays, parallel programming is achieved by increasing the number of processing elements in processor cores, increasing the number of processor cores itself and complicated parallel programming where programmer has the responsibility of allocating memory and synchronizing the communication between the processing elements as well as processor cores. It becomes increasingly difficult and expensive to design and produce shared memory machines with ever increasing number of processors. Increase in the number of processors is a major disadvantage when it comes to energy consumption. In this work, we present a new architecture for processor design based on pairwise balanced combinatorial interconnection of processing and memory elements. The proposed processor uses two operand instructions, so that the set of executable machine instructions is partitioned by these pairs. This kind of partition allows parallel processing of data-independent instructions. Since this partition is done at the compile time, the architecture extracts the instruction level parallelism without run-time overheads. We analyze and confirm the performance improvements through simulations. The suggested combinatorial arrangement gives set of architectures with various degrees of performance enhancement.

SummaryDriven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious. As a new type of computer architecture, computing-in-memory is an alternative approach to alleviate the von Neumann bottleneck. Here, we have demonstrated two kinds of computing-in-memory designs based on two-surface-channel MoS2 transistors: symmetrical 4T2R Static Random-Access Memory (SRAM) cell and skewed 3T3R SRAM cell, where the symmetrical SRAM cell can realize in-memory XNOR/XOR computations and the skewed SRAM cell can achieve in-memory NAND/NOR computations. Furthermore, since both the memory and computing units are based on two-surface-channel transistors with high area efficiency, the two proposed computing-in-memory SRAM cells consume fewer transistors, suggesting a potential application in highly area-efficient and multifunctional computing chips.

Abstract5G mobile systems and beyond are envisaged to provide very high throughput, to meet very strict requirements in terms of latency, and to support a very large number of devices in a very small area. Multiple‐input, multiple‐output (MIMO) systems can contribute to meeting these targets by enabling the concurrent transmission of a large number of information streams. In such MIMO systems, the choice of the corresponding required beamforming/precoding (in the downlink) and detection (in the uplink) algorithms can determine how much of the overall MIMO channel capacity and how much of MIMO's inherent capability to support multiple users we can exploit in practice. Linear beamforming and detection approaches are practical, but they highly underutilize the MIMO channel. Nonlinear methods can provide substantial gains, both in terms of throughput and connectivity, but their complexity increases exponentially with the number of concurrently transmitted information streams. This complexity, together with the soon‐to‐be‐reached plateau in the speed of processors, urges a paradigm shift toward massively parallel signal processing for wireless communications systems. Ideal parallelization methods should be scalable to any number of available processing elements, generic, adjustable to the transmission conditions, and transparent to the choice of the implementation platform. Promising parallelization algorithms in this direction enable up to 70% throughput gains without changing the number of base‐station antennas and RF chains, and can substantially increase the number of connected devices, with processing latency requirements similar to those of linear approaches.

In this paper, a hierarchical resampling (HR) architecture has been presented for distributed particle filters (PFs). The proposed architectures decomposes the resampling step into two hierarchies, of which the first one, called intermediate resampling, is conducted consecutively among processing elements (PEs) the moment new particles and their weights are generated by each PE, and the second one, named unitary resampling, is performed sequentially after the whole intermediate resampling procedure and shared by all PEs. Compared with traditional distributed architectures, the HR architecture eliminates the particle redistribution step, and has such advantages as short execution time, high memory efficiency and well scalability.

With the advance of process technologies, delay variation becomes relatively larger. As a result, it becomes difficult to improve a performance such as a clock frequency in conventional worst-case design. A post-silicon approach is one of the promising approaches to overcome this serious problem. In this paper, two techniques are introduced and combined: The first technique, named the stall insertion, is to insert pauses, and shift all the following operation schedules by one or more control steps. The second technique, named the timing skew adjustment, is a temporal difference of the arrival of clock signals at registers. This paper proposes a novel datapath which is tuned by the stall insertion with the timing skew adjustment after the fabrication. The tuned datapath in proposed design can be expected to operate correctly with minimum degradation while keeping clock period unchanged. Since the stall insertion degrades latency, the stall minimization problem is formulated incorporating with timing skew optimization. Two solution algorithms are presented: one is a mixed integer linear programming (MILP) formulation, and the other is the repetition of skew adjustability test. Experimental results show the effectiveness of our MILP.

The execution speed of the FPGA processing elements are compared to the microprocessor processing elements in the SRC 6 reconfigurable computer using the following algorithms for sorting: quick sort, heap sort, radix sort, bitonic sort, and odd/even merge. The results show that, for sorting, FPGA technology may not be the best processor choice and that factors such as memory bandwidth, clock speed, algorithm computational density and an algorithm's ability to be pipelined all have an impact on FPGA performance.

Horizon is a shared-memory multiple-instruction-stream-multiple-data-stream architecture currently under study. The performance of one Horizon processing element (PE) is quantified by user operations per instruction, the instructions per tick, and the basic clock rate. Assuming there is sufficient parallelism within a problem, the performance of one PE is multiplied by the number of PEs contained in the Horizon system. For a 256-PE Horizon the expected sustained performance is on the order of 50 billion user operations per second for problems with sustained parallelism of 8000 to 12000 instruction streams.

Variable magnetic flux motors have been proposed to achieve high-efficiency operation over a wide drive range ranging from high torque to high-speed. This paper clarifies the high efficiency area expansion effect of a variable flux motor with a magnetic composite material inserted in the rotor. To achieve the effect of enlarging the maximum efficiency range, this motor uses magnetic composite materials with much lower saturation magnetic flux density and iron loss than electromagnetic steel plate. This paper reports the magnetic and mechanical properties of the magnetic composite material using Fe–Si–Al alloy, considering low iron loss. The simulation results clarified the variable magnetic flux characteristics for reducing loss at high-speed rotation by actively utilizing the magnetic saturation region of the magnetic composite material. The efficiency improvement in the high-speed region is attributed to the suppression of spatial harmonics without significantly reducing the q-axis inductance. Furthermore, the proposed motor achieves both the expansion of the high-efficiency range and relaxation of mechanical stress by increasing the thickness of the bridge part adjacent to the permanent magnet.

With the wide application of autonomous mobile robots (AMRs), the visual inertial odometer (VIO) system that realizes the positioning function through the integration of a camera and inertial measurement unit (IMU) has developed rapidly, but it is still limited by the high complexity of the algorithm, the long development cycle of the dedicated accelerator, and the low power supply capacity of AMRs. This work designs a reconfigurable accelerated core that supports different VIO algorithms and has high area and energy efficiency, precision, and speed processing characteristics. Experimental results show that the loss of accuracy of the proposed accelerator is negligible on the most authoritative dataset. The on-chip memory usage of 70 KB is at least 10× smaller than the state-of-the-art works. Thus, the FPGA implementation’s hardware-resource consumption, power dissipation, and synthesis in the 28 nm CMOS outperform the previous works with the same platform.

In this paper, firstly, we have calculated the delay through an ideal RLC transmission line model, without the driver and the load impedance. This yield's to the transform voltage and current equations governing the system response by incorporating appropriate boundary conditions for interconnect delay analysis. Two port parameters in terms of ABCD matrix are obtained. Further we considered a practical transmission line with driver and load to find the relation between the transform input and output voltage response in s-domain. The relation thus obtained is applied to step input system and the transient response for it in time domain is obtained using inverse Laplace transform. Our main objective is to find the shape function of a wire which minimizes delay for RLC circuit. Although the problem has been studied under the Elmore delay model, it is only a rough estimate of the actual delay and more accurate estimation of the actual delay should be used to determine the wire shape function. The use of transmission line model in our study gives a very accurate estimate of the actual delay. Previous studies under Elmore delay model suggest that exponential wire shape function to be of the form f(x)=ae−bx. By solving the diffusion equation, we derive the transient response in the time domain as a function of a and b for step input. The coefficients a and b are determined so that the actual (50% delay) is minimized.

In the ray tracing method, each pixel can be computed independently. Therefore, when the ray tracing algorithm is implemented on a parallel computer, a group of pixels is usually assigned to each element processor. The element processor must have all the environment data and object data for the rendering. When there are too many objects for local memory, a distorted image will be generated. In solving this problem, to date, the necessary data had to be transmitted. However, when the number of element processors is increased, efficient rendering cannot be expected because of communication overheads. This paper proposes a hybrid parallel ray tracing algorithm that combines pixel-parallel and object-parallel ray tracing. As this algorithm inherits the advantages of pixel-parallel ray tracing, high efficiency can be achieved even on a parallel computer using a large number of element processors.