Rewired retiming for free flip-flop reductions without delay penalty

Interconnect delays represent an increasingly dominant portion of overall circuit delays. During timing-driven physical synthesis process, timing analysis is repeatedly performed over several hundred thousand components. Thus, fast and accurate estimation of interconnect delays is crucial. Traditionally, lumped and elmore delay models have been widely used for computing interconnect delays in physical synthesis due to their computational efficiency. However, these delay models are known to be inaccurate since they ignore slew and resistive shielding effects. In this paper, we propose a new iterative refinement based delay estimation approach that considers resistive shielding along with driver slew. Experimental results show that the proposed approach gives not only highly accurate results for far end RC-line delays but also compares very favorably to more difficult to match source end delays and source slews. In addition, use of the proposed delay model in physical synthesis yields significant performance improvement on several large industrial ASICs.

In this paper, firstly, we have calculated the delay through an ideal RLC transmission line model, without the driver and the load impedance. This yield's to the transform voltage and current equations governing the system response by incorporating appropriate boundary conditions for interconnect delay analysis. Two port parameters in terms of ABCD matrix are obtained. Further we considered a practical transmission line with driver and load to find the relation between the transform input and output voltage response in s-domain. The relation thus obtained is applied to step input system and the transient response for it in time domain is obtained using inverse Laplace transform. Our main objective is to find the shape function of a wire which minimizes delay for RLC circuit. Although the problem has been studied under the Elmore delay model, it is only a rough estimate of the actual delay and more accurate estimation of the actual delay should be used to determine the wire shape function. The use of transmission line model in our study gives a very accurate estimate of the actual delay. Previous studies under Elmore delay model suggest that exponential wire shape function to be of the form f(x)=ae−bx. By solving the diffusion equation, we derive the transient response in the time domain as a function of a and b for step input. The coefficients a and b are determined so that the actual (50% delay) is minimized.

At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.

This paper presents a high-level synthesizer to map a complete program efficiently on a dynamically reconfigurable processor (DRP). Initially, we introduce our DRP architecture, which is suitable for control-intensive programs since it has a stand-alone finite state machine that switches “contexts” consisting of many processing elements (PEs). Then, we propose three new techniques optimized for our DRP. Firstly, we explain how synthesized control steps are mapped onto the contexts. Several control steps are combined as a context to utilize PEs efficiently since each control step does not require the same amount of operational units. Secondly, we describe a modulo scheduling algorithm for loop pipelining, considering both spatial and time dimensions of our DRP. Lastly, we explain a scheduling technique to optimize clock frequency, which can take advantage of multiplexer, wire and routing switch delays. We have demonstrated a JPEG-based image decoder example to evaluate our methods. Experimental results show that high area efficiency is achieved by balancing the number of PEs between contexts. Despite an overall increase in performance on pipelining of 3.6 times that without pipelining, the number of operational units increased by a factor of 2.2. The clock frequency is maximized with accurate delay estimation.

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

3-D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. In this paper, we investigate the interconnect distributions of 3-D circuits. We divide the 3-D interconnects into horizontal wires and vertical wires and derive their wire-length distributions, respectively. Based on the stochastic wire-length distributions, we calculate 3-D circuit interconnect delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters needed, and dramatically improve the performance. With 3-D structures, a circuit can work at a much higher clock rate (double, even triple) than with 2-D. However, we also show that the impacts of vertical wires on chip area and interconnect delay may limit the number of device layers that we can integrate.

Flip flop is a fundamental electrical design component. Most electrical designs incorporate memory and their corresponding designs. The consumer electronics or end users need mobility and extended battery backup to enhance design performance. The focus on any parameter in the system is to maximize the performance of the design. Here the task is to reduce the energy use of flip flop. Due to the increased frequency clock delivered to the networks within the design, the edge or level triggered by a flip flop will contribute to power consumption. Due to the short circuit power consumption between ground and Vdd, the static design of the flip flop will increase power consumption. The flip flop is dynamically designed and implemented, leading to higher leakage power. Dynamic clock implementation helps for short-circuit power avoidance. It also provides greater download channel to the ground from output. The clocking system also demands more power. With the TSPC technology and output feedback, the suggested mechanic will increase the performance of the flip flop and establish the Pull-up network. The PMOS that contains the output node X value. The use of an additional NMOS transistor to draw the output value down to the ground, regardless of the input, so that the input runs on the discharge path that improves power, however the pulsed clock which has a smaller width than normal clock as well about 15% high.

A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient (SET) tolerance is demonstrated by simulations using it in a radiation hardened by design (RHBD) master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element incorporates redundancy to mask long transients, which would otherwise limit the circuit hardness. Two FF layouts using the proposed delay element are used in synthesis and auto-place and route experiments to confirm overall power, performance, and density. The first (interleaved) version uses a multi-bit cell interleaving the constituent circuits of four FFs. The second (inline) version interleaves the master and slave circuits to achieve high density while maintaining adequate critical node separation. The latter is shown to be more power efficient and the former is more robust to multiple node collection.

Power dissipation is becoming a prime design constraint in VLSI systems. The new key words for evaluating a design's performance are low power and high speed. This requires an overall system design review that considers suitable algorithms, architectures, circuits, and technology. In synchronous systems, the clocking network sets the frame that contains the whole design. It must be simple and robust. Power consumption in the clock distribution network has usually been a substantial part of the system total power consumption. New true single phase latches and flip flops are presented that are slope-insensitive, fast, and have data dependent power consumption. Flip flops are presented that work between DC and 1.7 GHz clock frequencies in a 1 /spl mu/m CMOS technology. Methods are given that result in power saving in the clock system by reducing the clock rate by half for the same data throughput on the system level.

With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of authentic chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme, where all combinational blocks function within one clock period, so that a netlist of combinational logic gates and flip-flops is sufficient to duplicate a design. In this article, we propose to invalidate the assumption that a netlist completely represents the function of a circuit with unconventional timing. With the introduced wave-pipelining (WP) paths, attackers have to capture gate and interconnect delays during reverse engineering, or to test a huge number of combinational paths to identify the WP paths. To hinder the test-based attack, we construct false paths with WP to increase the counterfeiting challenge. The experimental results confirm that WP true paths and false paths can be constructed in benchmark circuits successfully with only a negligible cost, thus thwarting the potential attack techniques.

For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform place and route and back-annotate the interconnection delays. A set of potentially optimal clock periods are chosen by evaluating 'critical' paths to minimize the dead time associated with operations. Finally, the controller costs at these clock periods along with the execution times decide the optimal clock period. Extensive experimental results on data paths synthesized from high-level synthesis benchmarks establish both the utility as well as the efficiency of our approach.

As nano-scale technology is widely adopted, minimizing the interconnection delay has become one of the most critical issues in designing high performance systems. To achieve fast timing closure, it is very important to estimate the interconnection delay accurately at an early design stage. In this paper, we propose a novel timing driven force-directed floorplanning technique using an efficient incremental static timing analyzer. Our proposed floorplan framework contains a fast and accurate interconnection delay estimator which is very important to obtain an excellent floorplan. The proposed timing methodology has been implemented as a part of a commercial floorplanning tool called Pillar-DP from Entasys Design Inc. We carried out experiments on several benchmarks to show the effectiveness of our approach. The experiment results show that our tool is valuable in generating a near optimal floorplan within a reasonable amount of time.

This paper presents a high performance, energy efficient implicit pulsed triggered flip flop based on direct coupled pass transistor (DCPT) approach. This approach directly couple input D to output Q of the flip flop to alleviate the worst case delay. It reduces input to output travelled path hence reduces D-to-Q delay and power consumption. It also includes an extra NMOS for latch designing to reduce the crossbar current. The simulation results presented are obtained by using SAED90nm CMOS technology with supply voltage 1V at 25°C temperature. It operates at 500MHz of clock frequency. By this technique it improves D-to-Q delay by 2% and power-delay-product by 22% for the proposed implicit pulsed flip flop.

Global interconnects are widely acknowledged as a limiting factor in future on-chip designs. Novel interconnect driving techniques like multi-level signaling have been proposed to improve performance of on-chip interconnects. This paper presents the impact of process-induced parameter variation on multi-level signaling system for on-chip interconnects. The effects of parameter variations is analyzed by Monte Carlo simulations and parameter sensitivity analyses. Monte Carlo analyses show that the threshold voltage, effective gate length and supply voltage are the key parameters that influence interconnect delay and total average power. It also shows that the interconnect delay and total average power with multi-level signaling for 10 mm line in 100 nm technology are normally distributed with a standard deviation of around 7.8% and 14.55% respectively. Individual parameter sensitivity analyses show that the total average power is most influenced by threshold voltage and is least influenced by drain/source parasitic resistance and thickness of oxide. The impact of different technologies, which include 180 nm, 130 nm and 100 nm are analyzed and it can be seen that the impact of individual device variation on delay and power reduces as technology scaled down. Yield of high performance and low power bins in 180 nm technology under process variations is 30%, yield of high performance bins is 23.2% and yield of low power bins is 36.1%.

Multiply-accumulate is an important and expensive operation. It is frequently used in digital signal processing and video/graphics applications. As a result, any improvement in the delay for performing this operation could have a positive impact on clock speed, instruction time and processor performance. In this paper, we show how, by extending our view of a parallel multiplier, we can apply recent innovations in parallel multiplier design to multiply-accumulators. This application results in multiply-accumulators that are as fast as multipliers of the same size (these multipliers have been shown to result in provably optimal delays faster than current designs). This allows a single (optimal multiply-accumulate) circuit to be used for both operations without delay penalty. As a result, multiply-accumulate can be efficiently and effectively implemented as an instruction in RISC CPUs. Additionally, the circuit design reduces the number of devices needed over current fast multiplier designs, so that real estate and power savings also result.