High performance code compression architecture for the embedded ARM/THUMB processor

The ARM processor is a dual width ISA processor that provides a 16-bit Thumb instruction set in addition to the 32-bit ARM instruction set. The compromises made in designing the Thumb instruction set leads to significantly increased instruction counts. This increase is in part due to the fact that only half of the register file is visible to most instructions in Thumb code. In this paper we address this inefficiency by providing a new instruction, the SetMask instruction, using which the compiler can change the visible subset of registers at any program point. Thus, through the use of this instruction the compiler can make use of all registers in all instructions. We present compiler techniques for allocating invisible registers and introducing SetMask instructions in a manner that the number of introduced instructions is minimized so that the increase in code size is insignificant. We implement this new instruction using the dynamic instruction coalescing framework which enables the SetMask instruction to have zero execution time cost. Our techniques eliminated 11.7% of MOV instructions from Thumb code while causing negligible code size increase.

In the embedded domain, memory usage and energy consumption are critical constraints.Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.

The ARM processor core is a leading processor design for the embedded domain. In the embedded domain, both memory and energy are important concerns. For this reason the 32 bit ARM processor also supports the 16 bit Thumb instruction set. For a given program, typically the Thumb code is smaller than the ARM code. Therefore by using Thumb code the I-cache activity, and hence the energy consumed by the I-cache, can be reduced. However, the limitations of the Thumb instruction set, in comparison to the ARM instruction set, can often lead to generation of poorer quality code. Thus, while Thumb code may be smaller than ARM code, it may perform poorly and thus may not lead to overall energy savings.

The effects of instructional set on social skills performance among psychiatric inpatient children

The size of the embedded software is increasing at a rapid pace. Often, the task of designing hardware that meets a lot of functionality needed in software became a challenging process and it needs more time for projecting. Then, the compression code is a way to reduce this problem. This paper presents an innovative and efficient approach to code compression. Our method reduces code size by up to 31% (including all extra costs). We performed simulations and analyzes, using the applications from benchmark MiBench and use two embedded processors (ARM and MIPS). Our method is orthogonal to approaches that take into account the particularities of a given instruction set architecture, becoming an independent method for any specific architecture. We have implemented the decompressor using VHDL and FPGA and we obtained only one clock from decompression process.

The paper presents the work that has resulted in the sum and threshhold (SAT) processor; a dedicated hardware implementation of a binary neural image processor. The SAT processor is aimed specifically at supporting the ADAM algorithm and is currently being integrated into a new version of the C-NNAP parallel image processor. The SAT processor performs binary matrix multiplications, a task that is computationally complex for a CPU with a standard instruction set. It can perform the matrix multiplication and thresholding between 100 and 200 times faster than the DSP32C that uses an in-house produced dedicated coprocessor. This speed-up will allow the SAT to process images of up to 220*220 pixels at 25-Hz frame rates.

This paper sets forth the need for a standard set of instructions in the safe handling and use of explosives in the geophysical industry. It suggests the appointments of an agency, such as the Bureau of Mines, to collect data regarding accidents and near-accidents in which explosives were involved, the agency also to analyze the data that are submitted and compile from the data a standard set of instructions. Several accidents which occurred while explosives were being used by the geophysical industry and which were reported to the Bureau of Mines during the last three years are discussed and analyzed in this paper. Although the accidents analyzed in this paper were not all of the accidents that occurred in the geophysical industry, they cost the industry over $235,000 and the lives of 5 men, in addition to permanent injuries to several members of the geophysical crews. The author believes that if a standardized set of instructions were compiled and used by the geophysical industry, most of the explosives accidents could be prevented. Moreover, these instructions would improve the efficiency of crews when the men are shifted or new men are employed.

The present simulation study was designed to evaluate the accuracy of the computerized Minnesota Report in identifying faked response sets on the Minnesota Multiphasic Personality Inventory (MMPI-2). The Minnesota Report is being increasingly relied upon in forensic neuropsychological assessments to assist in identifying malingering. Three groups of 18 students were given different sets of instructions: fake-good, fake-bad, and the standard instructions. Of those participants instructed to fake-good, the classification rate was 94% with only one participant misclassified as providing a “normal” profile. Of those participants instructed to fake-bad, 100% were correctly classified by the Minnesota Report. Of those who completed the MMPI-2 under standard instructions 78% were classified as having “normal” profiles, whereas 22% were classified as faking-good. The value of the Minnesota Report in identifying fake-bad response sets was amply demonstrated, and it is such performances that may be helpful in detecting malingering in forensic evaluations.

Code density is of increasing concern in embedded system design since it reduces the need for the scarce resource memory and also implicitly improves further important design parameters like power consumption and performance. In this paper we introduce a novel, hardware-supported approach. Besides the code, also the lookup tables (LUTs) are compressed, that can become significant in size if the application is large and/or high compression is desired. Our scheme optimizes the number and size of generated LUTs to improve the compression ratio. To show the efficiency of our approach, we apply it to two compression schemes: ldquodictionary-basedrdquo and ldquostatisticalrdquo. We achieve an average compression ratio of 48% (already including the overhead of the LUTs). Thereby, our scheme is orthogonal to approaches that take particularities of a certain instruction set architecture into account. We have conducted evaluations using a representative set of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS, and PowerPC.

Code density is a major requirement in embedded system design since it not only reduces the need for the scarce resource memory but also implicitly improves further important design parameters like power consumption and performance. Within this paper we introduce a novel and efficient hardware-supported approach that belongs to the group of statistical compression schemes as it is based on Canonical Huffman Coding. In particular, our scheme is the first to also compress the necessary Look-up Tables that can become significant in size if the application is large and/or high compression is desired. Our scheme optimizes the number of generated Look-up Tables to improve the compression ratio. In average, we achieve compression ratios as low as 49% (already including the overhead of the Lookup Tables). Thereby, our scheme is entirely orthogonal to approaches that take particularities of a certain instruction set architecture into account. We have conducted evaluations using a representative set of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS and PowerPC.

The Personality Research Form (PRF) was administered to 40 male alcoholics under standard instructions (SI) and instructions to respond desirably (DI). When instructional sets were compared, 13 of the 22 PRF scales were significantly different. It was concluded that faking attempts in the desirable direction though producing statistically significant differences in group means, may not produce differences that actually make a difference in a practical sense.

The level of support for high level programming languages (HLPLs), despite the claim of support by some of the newly introduced microprocessors, is inadequate despite the falling (rising) cost of hardware (software). Computer systems that are to be used to run programs written exclusively in HLPLs have a need for a multiprocessor/multiarchitecture microprocessor design (M3D); the personal/desk-top computers are prime examples. The HLPLs that will be used in programming these systems will be grouped according to their structures. Each group of languages will require their own instruction set; the hardware and software needs will determine the type of architecture configuration, i.e. aspects such as: register-to-register, memory-to-memory, stack, or a combination of these. The overall system should be divided up into functional units, e.g. ALU, compiler/translator, etc. Each functional or subfunctional unit will be implemented in software, firmware, hardware, or a combination of these with implementation decision based on the speed criticality, cost, technology, and the need to modify the unit. This approach will lead to a cop-down-design, and will also reduce the semantic gap, software and system cost, and down-time.

This poster reports on factors that influenced the rapid adoption and implementation of the Massachusetts Youth Screening Instrument-version 2 (MAYSI-2) and the perceived consequences of routine MAYSI-2 mental health screening. Semi-structured interviews and focus groups were conducted with administrators, managers, and front-line staff in juvenile detention centers in three states (n=19). Results will allow us to better inform juvenile justice facilities regarding the conditions under which screening can more often result in increases in mental health services to youth entering the system and help guide future efforts to provide technology to juvenile justice programs in the interest of youths. InTRoduCTIon Recent evidence suggests that the prevalence of mental disorders among youths in the juvenile justice system is two to three times higher than youths in the general population. Within the past five years, mental health screening upon entry to a juvenile justice facility has become standard practice across the nation. We know more about the validity and reliability of mental health screening tools used in this context than we do about the factors that facilitate their implementation. If they are not implemented properly, their adequate validity is virtually lost. Effective screening procedures require attention to how they are put in place and how they actually function within juvenile justice facilities. Introduced in 2000, the Massachusetts Youth Screening Instrument—Second Version (MAYSI-2) is now the most widely used mental health screening tool in juvenile justice secure facilities in the U.S. The National Youth Screening and Assistance Project (NYSAP), funded by the MacArthur Foundation, provides technical assistance nationwide for juvenile justice programs implementing mental health screening. ConCluSIonS And ReCommendATIonS Findings regarding the first three research questions suggest the following recommendations: n Develop a policy that avoids repetitive administration of the MAYSI-2. n Use a standard set of instructions for completing the MAYSI-2 when introducing youths to the instrument. n Use a standard set of instructions when introducing youths to the MAYSI-2 or any other screening tool. n Develop policy and practice to assure legally and clinically appropriate uses of mental health screening data.

We present an architecture for compression/decompression of executable files running on embedded systems. Compression is important for memory reduction purposes; previous work on memory reduction for embedded systems has focused on compressing the instruction segment of executable code before execution and decompressing at runtime. Our work has shown that solely compressing the instruction segment is not enough as in many cases executable files contain large data areas that would benefit from compression as well. Compressing data areas presents new challenges to the embedded system designer; data can be modified during execution and therefore a fast compression algorithm and intelligent memory management are required as well. We propose a novel compression/decompression framework that can handle both instructions and data and show memory reductions over 50% while keeping performance degradation within 12%.

In embedded system design, memory is one of the most restricted resources, posing serious constraints on program size. Code compression has been used as a solution to reduce the code size for embedded systems. Lossless data compression techniques are used to compress instructions, which are then decompressed on-the-fly during execution. Previous work used fixed-to-variable coding algorithms that translate fixed-length bit sequences into variable-length bit sequences. In this paper, we present a class of code compression techniques called variable-to-fixed code compression (V2FCC), which uses variable-to-fixed coding schemes based on either Tunstall coding or arithmetic coding. Though the techniques are suitable for both reduced instruction set computer (RISC) and very long instruction word (VLIW) architectures, they favor VLIW architectures which require a high-bandwidth instruction prefetch mechanism to supply multiple operations per cycle, and fast decompression is critical to overcome the communication bottleneck between memory and CPU. Experimental results for a VLIW embedded processor TMS320C6x show that the compression ratios using memoryless V2FCC and Markov V2FCC are around 82.5% and 70%, respectively. Decompression unit designs for memoryless V2FCC and Markov V2FCC are implemented in TSMC 0.25-/spl mu/m technology.