Profile guided selection of ARM and thumb instructions

In the embedded domain, memory usage and energy consumption are critical constraints.Embedded processors such as the ARM and MIPS provide a 16-bit instruction set, (called Thumb in the case of the ARM family of processors), in addition to the 32-bit instruction set to address these concerns. Using 16-bit instructions one can achieve code size reduction and instruction cache energy savings at the cost of performance. This paper presents a novel approach that enhances the performance of 16-bit Thumb code. We have observed that throughout Thumb code there exist Thumb instruction pairs that are equivalent to a single ARM instruction. We have developed enhancements to the processor microarchitecture and the Thumb instruction set to exploit this property. We enhance the Thumb instruction set by incorporating Augmenting eXtensions (AX). A Thumb instruction pair that can be combined into a single ARM instruction is replaced by an AXThumb instruction pair by the compiler. The AX instruction is coalesced with the immediately following Thumb instruction to generate a single ARM instruction at decode time. The enhanced microarchitecture ensures that coalescing does not introduce pipeline delays or increase cycle time thereby resulting in reduction of both instruction counts and cycle counts. Using AX instructions and coalescing hardware we are also able to support efficient predicated execution in 16-bit mode.

The ARM processor is a dual width ISA processor that provides a 16-bit Thumb instruction set in addition to the 32-bit ARM instruction set. The compromises made in designing the Thumb instruction set leads to significantly increased instruction counts. This increase is in part due to the fact that only half of the register file is visible to most instructions in Thumb code. In this paper we address this inefficiency by providing a new instruction, the SetMask instruction, using which the compiler can change the visible subset of registers at any program point. Thus, through the use of this instruction the compiler can make use of all registers in all instructions. We present compiler techniques for allocating invisible registers and introducing SetMask instructions in a manner that the number of introduced instructions is minimized so that the increase in code size is insignificant. We implement this new instruction using the dynamic instruction coalescing framework which enables the SetMask instruction to have zero execution time cost. Our techniques eliminated 11.7% of MOV instructions from Thumb code while causing negligible code size increase.

The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. Our proposed memory compression architecture has showed a further size reduction of 15% to 20% on the THUMB code. In this paper we propose to use a high-speed data lossless hardware decompressor to improve the timing performance of the architecture. We simulated the architecture on the SimpleScalar platform and show that for some applications, the time overheads are limited within 5% of the original application.

Chapter 11 - The ARM Architecture

Multimedia systems, such as interactive broadcast and satellite radios, have increasingly been demanding higher performance CPUs and higher performance DSPs to process the received data in real-time. In many cases, the performance of a general-purpose processor is not adequate, and this creates a demand for a system-on-chip device that processes the multimedia tasks efficiently and independently. A device, which integrates TI DSP and ARM processor cores, is an ideal solution for implementing interactive multimedia systems. One concept proposed here, utilizing this device, is an interactive broadcast radio system where the analog radio broadcast signal is received and real-time MP3 data is encoded/decoded to enable time shifting capabilities such as hard disk recording, pause, fast forward, and rewind. This architecture also allows voice command recording of driving directions that enables productizing a low-cost navigation system.

Many sound effects such as Autotune are very popular among artists to be used in live concerts. However, latency problems may occur when using these effects. This latency may affect the artists negatively. Latency of audio processing in CPU-based systems is a significant issue and does not provide minimal worst-case latency values for many high-end musical devices to be used in live concerts. This paper investigates how to achieve a low-latency audio processing with hardware and software co-design methodology in FPGA-based systems by designing an application-specific system-on-chip (SoC) architecture containing a hardware accelerator to generate a sound effect. The accelerator is connected to an ARM processor core within a Zynq-based programmable SoC platform. The ARM processor core is responsible (1) to handle data movement operations, (2) to enable or disable the sound effect over captured audio signal and (3) to perform some of the operations of the sound effect algorithm. The sound effect algorithm is designed in MATLAB & Simulink and corresponding hardware is generated through the HDL Coder. Our main objective is to reduce the audio latency of sound effect processing from input to output by designing a sound effect-specific hardware IP core via MATLAB & Simulink and incorporating it on a custom SoC architecture. SoC solution is prototyped in ZedBoard that contains ZC7020 Zynq chip and this low-end embedded SoC system outperforms the CPU-based solution.

We address the problem of instruction selection in code generation for embedded DSP microprocessors. Such processors have highly irregular data-paths, and conventional code generation methods typically result in inefficient code. Instruction selection can be formulated as directed acyclic graph (DAG) covering. Conventional methods for instruction selection use heuristics that break up the DAG into a forest of trees and then cover them independently. This breakup can result in suboptimal solutions for the original DAG. Alternatively, the DAG covering problem can be formulated as a binate covering problem, and solved exactly or heuristically using branch-and-bound methods. We show that optimal instruction selection on a DAG in the case of accumulator-based architectures requires a partial scheduling of nodes in the DAG, and we augment the binate covering formulation to minimize spills and reloads. We show how the irregular data transfer costs of typical DSP data-paths can be modeled in the binate covering formulation.

Although many countermeasures have been developed for desktop and server environments, buffer overflows still pose a big threat. The same approach can be used to target mobile devices. Unfortunately, they place more severe limitations on countermeasures. Not only are the performance requirements at least as important, memory and power consumption need to be considered as well. Moreover, processors used in mobile devices generally are equipped with a different instruction set. Therefore countermeasures may not be ported easily. Multistack is an effective countermeasure against stack-based buffer overflows. It protects applications by using multiple stacks to separate possible attack targets from possible sources. However, its performance overhead will no longer be negligible on the ARMv7 platform (widely used on mobile devices) and it wastes too much memory, making it too costly for mobile applications. We propose 3 methods to reduce memory overhead up to 28% with only a 3.91% performance overhead.

CHAPTER 1 - Introduction

CPU contains the most critical technology of computer. At present, popular processors use not only X86 instruction set such as Intel and AMD, but also MIPS instruction set such as Loongson, Alpha instruction set such as Shenwei, and ARM instruction set such as Phytium. Aiming at the requirement of high performance computing and high bandwidth communication, a high performance server used four channel S2500 processors is proposed based on CC-NUMA parallel processing architecture. In the present paper, the characteristics of S2500 processor are analyzed, the typical operation mode of instruction pipeline is studied, and the topology of 4 way S2500 processors is proposed. While the parallel computing performance of the system is improved, TOE technology is applied to the system in order to minimize the occupancy of CPU resources in full-load communication of 10G Ethernet interface. By the test of comparing the computing performance of single processor and four channel processors, and the CPU occupancy rate of common network card and TOE network card, the results show that the server can achieve efficient parallel computing capability by using CC-NUMA architecture and 4 way S2500 processors. The TOE chip can guarantee 10G Ethernet communication capability while occupying CPU resources as little as possible. The designed system is suitable for application scenarios of high performance computing and high communication bandwidth.

This paper presents a novel compiler backend which generates assembly code for Synchronous Transfer Architecture (STA). STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for this architecture needs highly optimizing techniques. The compiler backend presented in this paper is based on Integer Linear Programming (ILP). Experimental results show that the generated assembly code consumes much less execution time than the code generated by traditional ways, and the code generation can be accomplished in acceptable time.KeywordsExecution TimeInteger Linear ProgramClock CycleOutput PortBasic BlockThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.

Specialized processors programmable in domain-specific languages are increasingly used in modern computing systems. The compiler-in-the-loop approach, based on the joint development of a specialized processor and a compiler, is gaining popularity. At the same time, the traditional tools, like GCC and LLVM, are insufficient for the agile development of optimizing compilers that generate target code of an exotic, irregular architecture with static parallelism of operations. The article proposes methods from the field of program synthesis for the implementation of machine-dependent compilation phases. The phases are based on a reduction to SMT problem which allows to get rid of heuristic and approximate approaches, that requires complex software implementation of a compiler. In particular, a synthesis of machine-dependent optimization rules, instruction selection and instruction scheduling combined with register allocation are implemented with help of SMT solver. Practical applications of the developed methods and algorithms are illustrated by the example of a compiler for a specialized processor with an instruction set that accelerates the implementation of lightweight cryptography algorithms in the Internet of Things. The results of compilation and simulation of 8 cryptographic primitives for 3 variants of specialized processor (CISC-like, VLIW-like and a variant with delayed load instruction) show the vitality of the proposed approach.

We propose a novel instruction compression scheme based on fine-grained programmable dictionaries. In its core is a compile-time region-based control flow analysis to selectively update the dictionary contents at runtime, minimizing the update overheads, while maximizing the beneficial use of the dictionary slots. Unlike in the previous work, our approach selects regions of instructions to compress at compile time and changes dictionary contents in a fine-grained manner at runtime with the primary goal of reducing the energy footprint of the processor instruction stream. The proposed instruction compression scheme is evaluated using RISC-V as an example instruction set architecture. The energy savings are compared to an instruction scratch pad and a filter cache as the next level storage. The method reduces instruction stream energy consumption up to 21 % and 5.5 % on average when compared to the RISC-V C extension with a 1% runtime overhead and a negligible hardware overhead. The previous state-of-the-art programmable dictionary compression method provides a slightly better compression ratio, but induces about 30 % runtime overhead.

RAIN1000Z1 is a high performance readout module we developed last two years. It is based on the ZYNQ architecture SOC chip from Xilinx and ZYNQ is the new architecture of FPGA with dual high performance ARM Cortex-A9 processors and high capacity programmable logic. We developed a series of readout system with the RAIN1000Z1 module based on ZYNQ architecture. For the crystal scintillator detectors, such as BC-501A liquid scintillator in a Teflon vessel we used for neutron background measurement in CJPL (China JinPing under-ground Lab) experiment, we developed a two channels 8-Bit 1GHz FADC readout system with RAIN1000Z1 module. With the two R1250 PMTs in the dual end of detector, the analog signals are send to FADC and the digital results is triggered and anticoincidence in the FPGA logic, the final triggered data is send to computer by gigabits Ethernet with ARM processor running Embedded Linux. HMCAD1511 from ADI is used for 8-Bit 1GSPS analog data converter, and the high speed, low jitter 1GHz clock is generated by LMK04803B from TI. With the benefit of high bandwidth and high performance inter connected HP bus between ARM processor (PS) and FPGA logic (PL), the FADC's data gathered by FPGA logic is buffered and transferred to the ARM processor's DDR3 SDRAM running at 1066MHz with CDMA function without many CPU time. The readout interface's data throughput can reach more than 600Mbps with gigabits Ethernet. In this paper, details of the hardware design and HDL design will be introduced.