High Performance Computing on Cluster and Multicore Architecture

We will start this exciting journey exploring the scientific domain of digital image processing with Raspberry Pi. To begin the journey, you must be comfortable with the basics of single board computers (SBCs) and with Raspberry Pi. This chapter discusses the definition, history, and philosophy behind SBCs. It compares SBCs to regular computers. Then it moves toward the most popular and best selling SBC of all time, the Raspberry Pi. By the end of this chapter, you will have adequate knowledge to set up your own Raspberry Pi independently. This chapter aims to make you comfortable with the basic concepts of SBCs and Raspberry Pi setup.

High performance computing (HPC) devices is no longer exclusive for academic,\nR&D, or military purposes. The use of HPC device such as supercomputer now\ngrowing rapidly as some new area arise such as big data, and computer\nsimulation. It makes the use of supercomputer more inclusive. Todays\nsupercomputer has a huge computing power, but requires an enormous amount of\nenergy to operate. In contrast a single board computer (SBC) such as Raspberry\nPi has minimum computing power, but require a small amount of energy to\noperate, and as a bonus it is small and cheap. This paper covers the result of\nutilizing many Raspberry Pi 2 SBCs, a quad-core Cortex A7 900 MHz, as a cluster\nto compensate its computing power. The high performance linpack (HPL) is used\nto benchmark the computing power, and a power meter with resolution 10mV / 10mA\nis used to measure the power consumption. The experiment shows that the\nincrease of number of cores in every SBC member in a cluster is not giving\nsignificant increase in computing power. This experiment give a recommendation\nthat 4 nodes is a maximum number of nodes for SBC cluster based on the\ncharacteristic of computing performance and power consumption.\n

Recent advances in large-scale experimental facilities ushered in an era of data-driven science. These large-scale data increase the opportunity to answer many fundamental questions in basic science. However, these data pose new challenges to the scientific community in terms of their optimal processing and transfer. Consequently, scientists are in dire need of robust high performance computing (HPC) solutions that can scale with terabytes of data. In this thesis, I address the challenges in three major aspects of scientific big data processing as follows: 1) Developing scalable software and algorithms for data- and compute-intensive scientific applications. 2) Proposing new cluster architectures that these software tools need for good performance. 3) Transferring the big scientific dataset among clusters situated at geographically disparate locations. In the first part, I develop scalable algorithms to process huge amounts of scientific big data using the power of recent analytic tools such as, Hadoop, Giraph, NoSQL, etc. At a broader level, these algorithms take the advantage of locality-based computing that can scale with increasing amount of data. The thesis mainly addresses the challenges involved in large-scale genome analysis applications such as, genomic error correction and genome assembly which made their way to the forefront of big data challenges recently. In the second part of the thesis, I perform a systematic benchmark study using the above-mentioned algorithms on different distributed cyberinfrastructures to pinpoint the limitations in a traditional HPC cluster to process big data. Then I propose the solution to those limitations by balancing the I/O bandwidth of the solid state drive (SSD) with the computational speed of high-performance CPUs. A theoretical model has been also proposed to help the HPC system designers who are striving for system balance. In the third part of the thesis, I develop a high throughput architecture for transferring these big scientific datasets among geographically disparate clusters. The architecture leverages the power of Ethereum's Blockchain technology and Swarm's peer-to-peer (P2P) storage technology to transfer the data in secure, tamper-proof fashion. Instead of optimizing the computation in a single cluster, in this part, my major motivation is to foster translational research and data interoperability in collaboration with multiple institutions.

Traditional forensic analysis of hard disks and external media typically involves a powered down machine and “dead analysis” of these devices. Forensic acquisition of hard drives and external media has traditionally been by one of several means: standalone forensic duplicator; using a hardware write-blocker or dock attached to a laptop, computer, workstation, etc., forensic operating systems that live boot from a USB, CD/DVD or virtual machines with preinstalled operating systems. Standalone forensics acquisition and imaging devices generally cost thousands of dollars. In this paper, we propose the use of single board computers as forensic imaging devices. Single board computers can provide a low budget forensic imaging solution that can be used in a lab, remote acquisition, or even be configured as portable imaging devices. This project tests different ARM processor based single board computers and the software available at the present time. The project includes image acquisition using a write-blocker, software write-blockers and without write-blockers to test the various configurations. The final results demonstrate clearly that ARM based single board computers can be used as low cost and low energy forensic imaging devices.

One of the most important metrics in measuring the performance of a database system is query response time, which is composed of I/O time and CPU time. I/O time is decided by the amount of data read/write from/to disks and how the data is located on disks. CPU time is decided by how the database system performs the query operations. So if we want to reduce the query response time we can reduce either I/O time or CPU time, or both of them. We know retrieving data from disks is much slower than retrieving data from main memory. Hence, one of the common ways to reduce I/O times is clustering data on disks so that queries will access only relevant data. This paper introduces an efficient algorithm, called AutoClust, for automatic database attribute clustering (or also called automatic database vertical partitioning) for single computers as well as cluster computers. It is based on closed item sets mined from queries and their attributes using association rule mining. The paper then presents experimental results comparing the performance of AutoClust with that of a baseline algorithm on both single computers and cluster computers using the TPC-H benchmark running on major commercial database systems. The experiments show that AutoClust has better query costs for both types of computers.

Numerous studies have shown that operating system (OS)noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for high performance computing (HPC),especially in multi-processor/core systems, most of them focus on 2- or 4-core systems. In this paper, we analyze the major sources of OS noise on a massive multithreading processor, the Sun UltraSPARC T1,running Linux and Solaris. Since a real system is too complex to analyze, we compare those results with a low-overhead runtime environment: the Netra Data Plane Software Suite (Netra DPS). Our results show that the overhead introduced by the OStimer interrupt in Linux and Solaris depends on the particular core and hardware context in which the application is running. This overhead is up to 30% when the application is executed on the same hardware context of the timer interrupt handler and up to 10% when the application and the timer interrupt handler run on different contexts but on the same core.We detect no overhead when the benchmark and the timer interrupt handler run on different cores of the processor.

In scientific computing, solving systems of linear equations is a very essential and widely used complex problem. Finding an optimal solution, using various algorithms, to these highly computation problems is very important. As the number of variables increases, the complexity of these problems also increases. These huge amounts of computations require High Performance Computing (HPC) systems, where efficient task distribution and accurate performance analysis are highly required on using these systems. In this paper, the computation performance using multicore architecture and Graphics Processing Units (GPUs) are compared with an analysis and expectations for the future of the new multicore systems. The number of cores in GPUs is extremely larger compared to the multicore architecture, while the memory overhead degrades the performance of GPUs dramatically. The expected scalability of the multicore system architecture tends to have better performance than GPUs.

Single board computer (SBC) is a compact built-in circuit with processing unit, memory access, and general purpose input and output units (Deep Learning Pipeline: Building A Deep Learning Model With TensorFlow [Authors: Hisham El-Amir, Mahmoud Hamdy]; Deep Learning with TensorFlow: Explore neural networks with Python [Authors: Giancarlo Zaccone, Md. RezaulKarim, Ahmed Menshawy]; Goodfellow et al., Deep learning, vol 1. MIT Press, Cambridge, 2016). The SBC is mainly compatible and portable in nature; these SBCs are the perfect option for ready-to-mount devices and for prototyping. Some of the famous SBCs in the present market include Raspberry pi, Ordroid, Jetson Nano, NVIDIA XAVIER, etc. Table 1 illustrates the comparison of important commonly used single board computers, capable to compute and import tensor flow packages. The NVIDIA SBCs are also enabled with GPU cores to make GPU coding Compute Unified Device Architecture (CUDA). The process runs in GPU framework for faster computation.

Approximately 1 in 8 women (13%) will be diagnosed with invasive breast cancer in their lifetime and 1 in 39 women (3%) will die from breast cancer [1]. The high mortality rate can be decreased by early and accurate screening. As the data shows the early detection correlates heavily with low mortality rates. Screening measures and guidelines differ from country to country, but can fit into two big groups, imaging techniques and biopsy. While generally women are guided to fast but less accurate imaging techniques, doctors generally refer to biopsy when the imaging techniques don’t give clear results. This paper uses convolutional neural networks, trained on a biopsy dataset neatly run on single board computer (Raspberry Pi) to advance computer aided diagnosis which would help doctors get a second opinion without referring to multiple doctors, doctors conjointly provide high false positive rates wherever healthy women area unit subject to false diagnosing, and might suffer from psychological and economic issues. The doctor would introduce some pictures of the biopsy cells to the system, which would return a report for the doctor, giving them estimation that the patient has malignant cells (deadly cancerous cells) or benign cells (not cancerous). Pathologists nowadays have 85% accuracy; creating a system that would increase the accuracy to 90% and decrease the false negatives would greatly increase early detection and survival chances for the patients.KeywordsBreast canceImage processingDeep convolutionnal neural networksRaspberry Pi 3 board

Due to various breakthroughs and advancements in machine learning and computer architectures, machine learning models are beginning to proliferate through embedded platforms. Some of these machine learning models cover a range of applications including computer vision, speech recognition, healthcare efficiency, industrial IoT, robotics and many more. However, there is a critical limitation in implementing ML algorithms efficiently on embedded platforms: the computational and memory expense of many machine learning models can make them unsuitable in resource-constrained environments. Therefore, to efficiently implement these memory-intensive and computationally expensive algorithms in an embedded computing environment, innovative resource management techniques are required at the hardware, software and system levels. To this end, we present a novel quality-of-service based resource allocation scheme that uses feedback control to adjust compute resources dynamically to cope with the varying and unpredictable workloads of ML applications while still maintaining an acceptable level of service to the user. To evaluate the feasibility of our approach we implemented a feedback control scheduling simulator that was used to analyze our framework under various simulated workloads. We also implemented our framework as a Linux kernel module running on a virtual machine as well as a Raspberry Pi 4 single board computer. Results illustrate that our approach was able to maintain a sufficient level of service without overloading the processor as well as providing an energy savings of almost 20% as compared to the native resource management in Linux.

In work, a real-time speed limit warning assistant system for drivers is presented. The proposed approach is able to produce optical and acoustic warnings by detecting speed limit signs simply processing captured images via a camera. The system developed can process by up to 7 frame per second on Raspberry Pi 2 single board computer.

This paper has proposed a new design of active lower limb orthosis which is called as oneDHALO (one-actuator Drive Hip and Ankle Linked Orthosis). The oneDHALO has a linking mechanism which connects both ankle joints with a medial hip joint and an actuator which drives the rotation angle. The joints linkage mechanism keeps feet always in parallel with the floor to avoid stumbling and assists swinging of the leg. In addition, one servo motor has been introduced to assist and control the movement constrained by the mechanism. To match the active movement to walking phase, optical sensors have been introduced at soles of the feet. The control device which consists of internal communication system, sensor interfaces and a single board computer (Raspberry Pi) is designed for all in one with the mechanical part of the orthosis. This presentation reveals the preliminary experimental results of the system to show the good points of the design.

We present a sampling hardware that can be used as a demonstration system for the triggerless random interleaved sampling method. The hardware is capable of acquiring sample-trains of lengths 2, 3 and 4 with a programmable inter-sample distance. Each sample-train consists of samples which originate from separate ADC channels. The whole system is supervised by a single board computer, Raspberry Pi, which also forms a communication interface for the system. The paper proposes a calibration method, which allows for reduction of the interchannel vo ltage offsets, equalization of the voltage gains in the individual ADC channels, as well as equalization of the inter-sample time distances.

The vehicle industry manufacturer is showing an increased interest in remote diagnostics by improving customer relationship management and commercial interest. The special nature of construction machines fact that architectures and applications proposed for vehicular communication are not optimized for these types of vehicles. This paper proposes a new remote diagnostic architecture based on IEEE 802.11n for construction machines communication to the infrastructure on site. The mobile Internet is used to transmit collected data to the central monitoring application. We discuss the possible network selection algorithms, mobility and security protocols that can be implemented on the On Board Units (OBU). The proposed architecture is based on Host Identity Protocol (HIP). This protocol introduces a Host Identifier (HI) for naming the endpoints and use intensive cryptographic operation for security and mobility management. Due to their minimal computing capabilities, many single board computers used as OBU themselves suffer from applications which need intensive CPU usage. Thus, a performance analysis of HIP, implemented on single board computers, is proposed by the end of this paper.

As a result of the increasing requirements of present and future computation intensive applications, there have been many fundamentally divergent approaches such as the Blue-Gene, TRIPS, HERO, Cascade spurred in order to provide increased performance at node level in supercomputing clusters. The design of the node architecture should be such that 'Cost-Effective Supercomputing' is realized without compromising on the requirements of the ever-performance hungry grand challenge applications. However, to increase performance at the cluster level, scalability and likewise tackling the mapping complexity across the large cluster of nodes becomes critical. The potential of such a node architecture can be fully exploited only with an appropriate cluster architecture. In an attempt to address these issues for efficient and Cost-Effective Supercomputing, we propose a novel paradigm for designing High Performance Clusters, in two papers. In paper-II, we discuss the design of operating system and cluster architecture. In this paper, we present a node architecture model based on the Memory In Processor paradigm and discuss the related architectural aspects (ISA, compiler, network interconnection etc). We provide a design space based on the proposed model for which a simulator is developed, with the help of which the performance of such a node architecture is outlined.