High Speed Error-Detection and Correction Architectures for Viterbi Algorithm Implementation

This paper presents a high throughput (1Gbps) and moderate area for constraint length K=3, code rate R=1/2 and four states (N=4) hard decision state parallel Viterbi decoder. The Add Compare Select (ACS) unit in path metric unit is designed to reduce the latency of ACS loop delay by using Modified Carry Look Ahead Adder and Digital Comparator. We also consider the design of Survivor Memory Unit (SMU) which combines the advantages of both Register Exchange method and Trace Back method, to reduce the decoding latency and total area of the Viterbi decoder. The proposed Viterbi decoder design is described using Verilog HDL and implemented in standard cell ASIC flow using Synopsys EDA tool. The design operation is verified by decoding the one million bits. The behavior of the decoder is verified by using Synopsys simulator and synthesized using Synopsys Design Compiler in 65nm CMOS technology library. The proposed decoder operates at 250MHz, supply voltage 1.32V and operating temperature range -40°C to 125°C. The ACS architecture achieves 67.07% improvement in reduction of latency compared to the conventional ACS architecture and achieves 1.235 Gbps throughput. The results show that, the Viterbi decoder architecture achieves 73.03% to 92.46% improvement in area as compared to the other architectures. This reduction in latency and area finds application in high data rate communication.

There has been widespread deployment of IEEE 802.11 wireless local area networks (LANs) because of high demand from mobile terminals, such as iPod and Android terminals. With the increasing energy consumption of the wireless LANs, the development of power saving technologies incorporated into the wireless LANs have become important. In wireless LANs, access points (APs) continuously consume the power regardless of the communication. Therefore, we have proposed the Radio-On-Demand (ROD) wireless LAN, which provides power saving schemes on the basis of the utilization of wireless LANs. In this study, we particularly focus on the power saving scheme of the APs, and propose the decentralized association management of ROD wireless LANs. In our scheme, an AP assigns associated stations (STAs) to new APs before switching to sleep mode. Simulation results show that the proposed scheme can realize sufficient power saving.

The method of decoding by Viterbi is used in areas like convolutional codes in digital TV, wireless local area networks, satellite communication, mobile relay. Also, the method is used in the development of Automatic Speech Recognition (ASR) and storage systems that work automatically. For Viterbi decoder-based architectures with low latency and complexity, which proposes error detection techniques that are effective. This paper explores the Viterbi algorithm which has two types of approaches for two types of subparts. Important aspects of any communication system are area/power consumption and throughput /efficiency. Minimization of these aspects is the need for an efficient system. This paper explores unwanted logical block reduction by modifying the present logical block. This paper explores signature-based approaches which result in acceptable efficiency. Also, another approach is used to achieve error detection in permanent and transient faults. This error detection is achieved by recomputing with encoded operands. Encoding means the use of shifting operation or the use of rotation operation. This approach makes the system slightly reliable and efficient.

Low proflle, light weight, easily mounted and broad bandwidth are the key charac- teristics for antennae designed for wireless applications. The microstrip antenna (MSA) suits the features mentioned except for its narrow bandwidth. The bandwidth of the microstrip antenna usually ranges from less than 1% to several percent. This paper experimentally investigates an alternative approach in enhancing the bandwidth of the microstrip antenna for the Wireless Lo- cal Area Network (WLAN) application operating at a frequency of 2.45GHz. The bandwidth enhancement technique which is studied is the Identical Dual Patch Microstrip Antenna with Air-Gap (IDMA). A bandwidth enhancement of more than 11% was achieved. Wireless applications have undergone rapid development in recent years. One particular wireless application that has experienced this trend is the Wireless Local Area Network (WLAN). The wireless application that is selected to be studied is the 2.4GHz to 2.5GHz frequency band which is based on the 802.11b WLAN standard. This frequency band is very popular due to its low cost. WLAN antenna requires being low proflle, light weight and broad bandwidth. The microstrip antenna suits the features very well except for its narrow bandwidth. The WLAN antenna should have a minimum bandwidth of 100MHz to fully utilize the WLAN band based on the 802.11b standard. The conventional microstrip antenna could not fulflll this requirement as its bandwidth usually ranges from less than 1% to several percent (1). Although the required operating frequency range is from 2.4GHz to 2.5GHz, at least double the bandwidth is required to avoid expensive tuning operations and to cause uncritical manufacturing. Therefore, there is a need to enhance the bandwidth of the microstrip antenna for WLAN applications. This paper investigates a technique which can enhance the bandwidth of the microstrip antenna without increasing the lateral size and the complexity of the microstrip antenna too much. The Identical Dual Patch Microstrip Antenna with Air-Gap (IDMA) bandwidth enhancement technique takes the advantage of using the air gap to lower the efiective permittivity and increase the total thickness of the microstrip antenna which is essential for bandwidth enhancement. This bandwidth enhanced microstrip antenna can be deployed for the WLAN application operating at a frequency of 2.45GHz. 2. SIMULATED AND MEASURED RESULTS OF THE SINGLE-LAYER MICROSTRIP ANTENNA

One of the uses of approximate circuits is machine learning (ML) and with the help of inexact logic minimization as well as through probabilistic pruning, these approximate computing circuits can be implemented. Nowadays, these approximate circuits have been widely explored due to their essential factors such as compact silicon areas well as low power consumption in movable devices. This research work shows how a 4:2 compressor can be designed using inexact logic minimization and thereby reversing a few bits of the output to ensure efficiency as well as accuracy. The average area, propagation delay as well as the average power of the proposed 4:2 compressor is been calculated and are employed in the 8 × 8 and 16x16 Dadda multiplier and truncation and rounding-based scalable approximate multiplier (TOSAM). Using Vivado Design Software Systems in 45nm technology, all the simulations were carried out and the MATLAB tool make use of error analysis to distinguish between precise as well as approximate proposed circuits. This work is mainly concentrated on the design of exact and approximate multipliers and measures the error between them and minimization of this error using the Machine Learning approach and finally validated the results on the Artix-7 FPGA development board of part XCA7CSG324_110t, the partial products which are generated by multipliers are added using 4:2 compressor adder. In the case of digital processing at nano-metric scales, approximate or inexact computing is considered one of the important examples. For computer arithmetic designs, inexact computation plays a significant role, and the new approximate 4:2 compressors are used in a multiplier that is based on TOSAM. These architectures mainly depend on various compression aspects to enable inaccuracy in computing which is described as error rate and is also referred to as normalized error distance which is used to satisfy circuit-based figures of merit, the number of transistors, delay as well as consumption of power. For a Dadda multiplier, four distinct approaches for exploiting the suggested approximation compressors are designed as well as evaluated. The usage of approximate multipliers for image processing, as well as a wide range of simulation results, are presented in this work. When contrasted to an accurate design, the proposed designs achieve a substantial reduction in the number of transistors, power dissipation as well as delay. Furthermore, the presented multiplier models exhibit outstanding image multiplication capabilities in terms of average normalized error distance as well as peak signal-to-noise ratio that is more than 50dB for the analyzed image samples. The proposed ML-based digital system has been developed in Vivado Design Suite and synthesized which is designed using Verilog HDL. Based on obtained results, 17% reduction in power, 21% reduction in latency, and 33% improvement in throughput.

Examines the effect of radio capture on the performance of radio frequency wireless local area networks (LANs). In many wireless LANs, multiple remote stations may simultaneously attempt to transmit data packets. Due to the capture effect, differences in received power levels can result in the successful reception of a packet in the presence of contending transmissions. The authors compare several types of radio capture models and investigate their effects on the slotted Aloha protocol, which is a component protocol of more complex multiple access protocols that are used in wireless LANs. Specifically, they analyse a vulnerability circle capture model as well as a more detailed model that includes the cumulative effect of the interference power generated by multiple contending remote stations. The effects of Rayleigh fading, shadowing, and different spatial distributions of remote stations are also considered. >

During the last two decades, wireless communication has been revolutionized by near-capacity error-correcting codes (ECCs), such as turbo codes (TCs), which offer a lower bit error ratio (BER) than their predecessors, without requiring an increased transmission energy consumption (EC). Hence, TCs have found widespread employment in spectrum-constrained wireless communication applications, such as cellular telephony, wireless local area network, and broadcast systems. Recently, however, TCs have also been considered for energy-constrained wireless communication applications, such as wireless sensor networks and the ‘Internet of Things.’ In these applications, TCs may also be employed for reducing the required transmission EC, instead of improving the BER. However, TCs have relatively high computational complexities, and hence, the associated signal-processing-related ECs are not insignificant. Therefore, when parameterizing TCs for employment in energy-constrained applications, both the processing EC and the transmission EC must be jointly considered. In this tutorial, we investigate holistic design methodologies conceived for this purpose. We commence by introducing turbo coding in detail, highlighting the various parameters of TCs and characterizing their impact on the encoded bit rate, on the radio frequency bandwidth requirement, on the transmission EC and on the BER. Following this, energy-efficient TC decoder application-specific integrated circuit (ASIC) architecture designs are exemplified, and the processing EC is characterized as a function of the TC parameters. Finally, the TC parameters are selected in order to minimize the sum of the processing EC and the transmission EC.

There has been a tremendous increase in the use of wire/wireless Local Area Networks (LAN) with different network configurations. Therefore, it is vital to have an accurate and a reliable generic platform to enable network developers, managers, security mangers, researchers, and students evaluating and investigating the performance of LANs of different technologies and configurations. Many network simulators have been developed throughout the years, such as: the Optimized Network Engineering Tool (OPNET), the Network Simulator (NS), the Global Mobile Simulator (GloMoSim), etc. One of the most widely-used and powerful general-purpose network simulators is OPNET, which is an object-oriented simulation environment. This chapter provides two walk through tutorials on using OPNET IT Guru (Academic Edition of OPNET) for wire/wireless LANs simulations. These tutorials demonstrate in step-by-step fashion, the procedures of initiating new simulation, setting up the simulation parameters, running the simulation, and viewing the results. The first tutorial (Tutorial #1) simulates a wired LAN of 10 computers and one server connected to a single switch, and the second tutorial (Tutorial #2) simulates a wireless ad hoc network of 10 mobile nodes and one server. This chapter demonstrates that OPNET IT Guru is a powerful tool that can be used by a range of professional users to simulate, evaluate, and investigate the performance of wire and wireless LANs. Moreover, it encourages and helps students to easily perform network simulation for better understanding of the network performance under different network conditions.

Data transmission over the wireless transmission channel is adversely affected by attenuation, distortion, interference, and noise, that hampers the ability of the receiver to correctly receive the transmitted message signal. Thus error detection and correction methods are implemented to mitigate these effects. Convolution encoder is one such channel encoding technique used at transmitter end for deep space and wireless communication whereas at receiver end the Viterbi decoder decodes the encoded data. Viterbi algorithm is based on principles of maximum likelihood where the optimal trellis path is identified that is followed at the encoder using cumulative hamming distance. This paper presents an SoC based Hardware-Software codesign approach of implementing the Viterbi Decoder along with the entire communication system comperising of random binary pattern generator, convolution encoder, QPSK modulator, QPSK demodulator and quantizer built on a Zynq-7000 All Programmable SoC chip. The blocks are designed using Verilog HDL (Hardware Description Language) using the tools Vivado IDE (Integrated Development Environment) 2017.4 by Xilinx and HDL coder toolbox of MATLAB 2018 $a$ by MathWorks. Simulink model of the communication chain is implemented to simulate the design considering the effect of AWGN (Additive White Gaussian Noise) through the channel and then the partial design is translated to be implemented on a Zynq-7000 AP SoC. This design can find potential applications in Satellite communication, SDR (Software Defined Radio).

A Wireless Local Area Network (WLAN) is a type of Local Area Network (LAN) that uses high frequency radio waves rather than wires to communicate and transmit data [1]. It is a flexible data communication system implemented as an extension to or as an alternative for, a wired LAN. It provides large companies the option to connect the current wired networks to the wireless network without any problems and gives user the option to use any kind of applications regardless of its source or vendors [2]. As data sharing is sometimes slow or worst slowness due to the performance of the WLAN which is a key factor in spreading and usage of such technologies. Hence it is necessary to identify the quality of the wireless connection and how to improve the communication through the WLAN. Therefore, in this paper, Evaluating and Improving Wireless LANs Performance has been proposed to address mains parameters as Wireless LAN performance indicators and then to propose some methods to improve the performance of WLAN connection via OPNET Modeler 9.1., an advanced network simulator.

This paper introduces a wirelessly powered scattered neural recording wearable system that can facilitate continuous, untethered, and long-term electroencephalogram (EEG) recording. The proposed system, including 32 standalone EEG recording devices and a central controller, is incorporated in a wearable form factor. The standalone devices are sparsely distributed on the scalp, allowing for flexible placement and varying quantities to provide extensive spatial coverage and scalability. Each standalone device featuring a low-power EEG recording application-specific integrated circuit (ASIC) wirelessly receives power through a 60 MHz inductive link. The low-power ASIC design (84.6 µW) ensures sufficient wireless power reception through a small receiver (Rx) coil. The 60 MHz inductive link also serves as the data carrier for wireless communication between standalone devices and the central controller, eliminating the need for additional data antennas. All these efforts contribute to the miniaturization of standalone devices with dimensions of 12 × 12 × 5 mm3, enhancing device wearability. The central controller applies the pulse width modulation (PWM) scheme on the 60 MHz carrier, transmitting user commands at 4 Mbps to EEG recording ASICs. The ASIC employs a novel synchronized PWM demodulator to extract user commands, operating signal digitization and data transmission. The analog frontend (AFE) amplifies the EEG signal with a gain of 45 dB and applies band-pass filtering from 0.03 Hz to 400 Hz, with an input-referred noise (IRN) of 3.62 µVRMS. The amplified EEG signal is then digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with a peak signal-to-noise and distortion ratio (SNDR) of 55.4 dB. The resulting EEG data is transmitted to an external software-defined radio (SDR) Rx through load-shift-keying (LSK) backscatter at 3.75 Mbps. The system's functionality is fully evaluated in human experiments.

The objective of this report is to describe the implementation and pilot-test of an integrated wireless local area network (WLAN) system that incorporated the Planmeca Promax CCD based digital panoramic/cephalometric x-ray system, Dolphin(R) software, and multiple remote user units to increase the efficiency of data management by the residents in the Department of Orthodontics. The Department of Orthodontics of the New Jersey Dental School (NJDS) acquired the Dolphin cephalometric analysis software and the Planmeca Promax digital panoramic/cephalometric x-ray units on separate occasions. Dolphin has been in use for many years at this institution, the current version being 10, and the Promax was acquired in the Fall of 2002. The digital panoramic and cephalometric radiographs were acquired and stored separately in the Planmeca's Dimaxis database. During the incorporation of the WLAN, there was an opportunity to research and install the best available security system for the WLAN so it could be a network model for the other departments within the dental school and perhaps other dental schools around the nation. Digital radiographs, once obtained, can be stored locally or transmitted securely to remote locations via a local area network. This article describes the selection criteria and methodology that would optimize the transmission and retrieval of such images instantaneously on demand at chair side locations. This will not only save significant clinical time but will enhance the productivity of the clinic in the long run.

This work presents an efficient hardware realization of diamond search motion estimation algorithm using adder compressor units. The main advantage of this kind of hardware is its large quantity of processing modules (PM) which are employed to determine the sum of absolute difference distortion metric. Processing units are composed of large quantity of adders to calculate the summation of absolute difference (SAD). Incorporated 3:2 and 5:2 adder compressor units (ACU) are used in the processing units to achieve high computational speed and make the architecture compatible for high definition television videos. The adder compressor units are capable of parallel addition of eight addend data. The complete hardware is realized in Verilog HDL, functionally verified, and implemented on FPGA. Also, the design is synthesized using Synopsys RC design compiler of 90nm technology standard cell library as an application specific integrated circuits (ASIC) implementation. Simulation and synthesis results show that the implemented architecture for diamond search algorithm achieve best results when performance evaluation is done.

The application of WLAN (Wireless Local Area Network) technology in the healthcare industry has gained increasing attention in recent years. It provides effective and efficient sharing of health information among healthcare professionals in timely treatment of patients (Collaborative Health Informatics Centre, 2000; Whetton, 2005a). However, there is still a concern among healthcare professionals whether health information is shared safely with WLAN technology. The primary aim of this study is to explore factors influencing healthcare professionals’ adoption of WLAN security technology. This study was conducted in regional health settings in Queensland, Australia using a focus group discussion and a questionnaire survey in a mixed research methodology. The outcomes indicate that learning support, user technology awareness, readiness of existing system, and social influence, are four important factors in healthcare professionals’ adoption of WLAN security technology. The findings suggest that healthcare professionals prefer to be more informed and prepared on knowledge of WLAN security technology before they decide to adopt it in their work environment. Therefore, their awareness of what the technology can do and cannot do for them, and the support they could get in learning to use the technology, play a crucial role. The healthcare professionals are concerned with how readily their existing system could support WLAN security technology and how people important to them would influence their decision in adopting WLAN security technology. Future research should extend the study in three areas. Firstly, future study should examine factors in this study with more regional areas of Australia. Secondly, future research should also examine the relationship between the factors and the demographic variables. Finally, there is also the possibility of examining the adoption factors with other security technology in healthcare, such as the pairing of WLAN technology and biometric security.

Wireless local area network (WLAN) has changed the paradigm of communication and become ubiquitous. As the number of devices connected to wireless is increasing, it is therefore, essential to find vulnerabilities in the security of wireless networks. In this research WLAN security vulnerabilities are exposed in real time. WLAN security techniques (MAC filtering, Hidden SSID and WPA2) available to residential users were practically exploited. Tenda WiFi wireless access point was set up with MAC filtering, hidden SSID and WPA2 security mechanisms in different combinations in such a way as to add an additional layer of security to previous configuration. Kali Linux version 2017.1 was used as a platform to exploit WLAN networks in real time. In this research, the sensitive information broadcasted by WLAN was utilized to carry out attacks on wireless networks. A practical demonstration of exposing vulnerabilities in MAC filtering, Hidden SSID with MAC filtering and WPA2-PSK with hidden SSID and MAC filtering security mechanisms of AP was carried out in real time. It was observed that the existing security mechanisms were vulnerable. Researchers have exploited many security mechanisms of WLAN focusing upon a single parameter of WLAN security at a time. However, in this work, the three available security mechanisms were cascaded to produce a three layer security mechanism i.e. WPA2 with hidden SSID and MAC filtering. This cascaded model was exploited in real time.