High-speed rate estimation based on parallel processing for H.264/AVC CABAC encoder

The rate-distortion (R-D) optimized mode decision is very important to obtaining full benefit from various powerful coding tools in the most recent video coding standard, namely the high efficiency video coding (HEVC). In deciding a certain coding mode, the R-D optimality criterion takes into account both distortion and bit rate. The bit-rate is generally measured from the number of bits in the bitstream that context-adaptive binary arithmetic coding (CABAC) generates through performing a series of binarization, context modeling, interval subdivision, renormalization, outstanding bit handling, and context updating. Its simplification is important to reduce the high complexity of actual bit rate estimation by CABAC. This paper proposes the efficient estimation of output bits by counting only the number of generated binarized output of the binarization process in CABAC. The proposed method only executes binarization, without performing context modeling, interval subdivision renormalization, outstanding bit handling, or context updating. We evaluate the performances of the proposed method using HEVC reference software, and our experimental results verify that the proposed scheme is very effective in reducing the complexity of rate calculation. Compared to the HEVC reference software that performs all the CABAC execution steps, the proposed method shows an average saving in rate calculation time for all intra, low delay, and random access conditions of 55.29%, 41.05%, and 42.96%, respectively.

Hardware implementation of HEVC CABAC binarization/de-binarization

In High Efficiency Video Coding (HEVC), the computational complexity has been increased so that an Early SKIP mode decision method is proposed by using coded block flag of an inter prediction unit (PU) to speed up mode decision with BD-bitrate increase. In this paper, we propose a fast SKIP mode decision algorithm to speed up PU mode decision for HEVC in a rate-distortion (RD) optimization sense. It is based on an adaptive linear predictor for PU mode type and available neighboring SKIP mode units on the quad-tree partition structure in HEVC for adaptive RD optimization. Moreover, the proposed method consists of both local (neighboring PUs) and global (previous PUs in current frame) level schemes on each coding unit (CU) level. In this way, it is possible to exploit high correlations between the RD cost of SKIP mode and spatial characteristics of video sequences by using the distribution of SKIP mode and a linear RD cost predictor. Experimental results show that the encoding computational complexity can be reduced by an average of 36 % with threshold RD cost, when compared to that of the HM 12 reference software.

Ultra High Definition Television (UHDTV) imposes extremely high throughput requirement on video codec's based on High Efficiency Video Coding (H.265/HEVC). Context-based adaptive binary arithmetic coding (CABAC) is specified as the single operation mode for entropy coding in HEVC. Parallel and pipeline processing can be used to increase the throughput for higher performance and decrease the path delay. This paper proposes a pipeline and parallel CABAC decoder architecture adaptive to HEVC syntax elements, In order to reduce the critical path delay, we stored the RangeLps LUT and LZ LUT in the same memory and we exploit different techniques of optimization. The implementation can process 1,5 bins/cycle when operate at 133,31 MHz and improved high throughput of 200Mbin/s for parallel decoder and process 1.49 bins/cycle when operate at 134.2 MHz with throughput of 200Mbin/s for pipeline decoder. The critical path delay is optimized compared to the serial process and the architecture is coded using VHDL language, simulated and synthesized using Xilinx tools with virtex4 xc4vsx25-12ff668 card.

In this paper, we propose a full-hardware context-based adaptive binary arithmetic coder (CABAC) encoder, which is the entropy coding tool adopted in the main and higher profiles of the video coding standard H.264/AVC. All CABAC coding features are implemented in hardware (HW), and different coding modes including rate-distortion optimization (RDO) are fully supported. An efficient memory access scheme is also proposed to reduce context RAM access frequency, context RAM size, and operation delay for RDO context state backup and restoration. Constant throughput of 1 bin per cycle is achieved in different coding configurations. The CABAC encoder is physically implemented in 0.13 mum process, and its post-layout simulation can be run at 328 MHz. The chip takes up 1.41 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and dissipates 0.79 mW to support 720p60 HDTV real-time encoding in RDO-off mode. Compared to the state-of-the-art reference design, the most significant advantage of this design is that a full HW implementation of CABAC encoder is proposed, which minimizes the computation on the host processor and data transfer on the system bus. Power consumption is minimal compared to reference designs using the same technology.

H.264/AVC offers critical advantages over other video compression schemes at the price of increased computational complexity. The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binary coder, which is the last stage of the video coder. The module conforms to H.264/AVC High Profile and supports two binary coding modes: context adaptive binary arithmetic coding (CABAC) and context adaptive variable-length coding (CAVLC). The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. Five versions of the arithmetic coding path are developed to study the area/performance tradeoff related to parallel symbol encoding. The implementation results show that the parallel symbol encoding allows higher efficiency. The whole architecture of the binary coder is described in VHDL and synthesized for different configurations to show the implementation cost of some coding options. For both CAVLC and CABAC modes, the architecture achieves the similar throughput able to support HDTV in real time.

In this paper, we propose a selective encryption scheme with a chaotic encryption system for the High Efficiency Video Coding (HEVC) standard in which Context Adaptive Binary Arithmetic Coding (CABAC) is the only entropy coder for transform coefficient coding. Our method focuses on the binstrings of truncated rice with a context “p” (TRp) code suffix and kth order Exp-Golomb (k = p + 1) code suffix before Binary Arithmetic Coding (BAC) for the remaining absolute level coding, which is coded by the bypass mode in the entropy coding stage. The probability of symbols does not change and CABAC decoding has no effect after encryption. Several different YUV sequences are used for experimental evaluation of the proposed algorithm. Compared to previous researches, our approach has good protection for video information, which keeps a constant bitrate and format compatibility, and meantime it has a negligible impact on encoding performance.

Context-based adaptive binary arithmetic coding (CABAC) is a single entropy coding mode of the newest video coding standard, High Efficiency Video Coding (HEVC). Despite the high coding efficiency of CABAC, its data dependencies prevent effective parallelization, which also means limited throughput. Accordingly, during the HEVC standardization activity of entropy coding, both coding efficiency and throughput were considered. This paper highlights the key techniques that were proposed and adopted up to HEVC Draft International Standard (DIS). In addition, a new method is proposed for high throughput entropy coding. This method reduces the worst-case complexity of entropy coding without significant coding efficiency loss. From the experimental results, in terms of throughput improvement, we confirm that the proposed method reduces the number of context-coded bins up to 42.1 and 15.9 % on average.

This paper presents a hardware design of context-based adaptive binary arithmetic coding (CABAC) for the emerging High efficiency video coding (HEVC) standard. While aiming at higher compression efficiency, the CABAC in HEVC also invests a lot of effort in the pursuit of parallelism and reducing hardware cost. Simulation results show that our design processes 1.18 bins per cycle on average. It can work at 357 MHz with 48.940K gates targeting 0.13 μm CMOS process. This processing rate can support real-time encoding for all sequences under common test conditions of HEVC standard conforming to the main profile level 6.1 of main tier or main profile level 5.1 of high tier.

Nowadays, the use of real time video communication is growing with a rapid pace. For example, Search and Rescue (SAR) applications like earthquake rescue, avalanche victims, wildfire monitoring in highway and surveillance are some of the applications of real time video communication. Most of these video communications require secure transmission of signals. For real time video communication, the processing time is considered as the most important metric to be optimized. Thus, finding a simple and time efficient encryption technique for securing the transmitted data becomes mandatory. The motive behind this work is to design a system that can process the video signal in real time providing a secure communication. In this paper, we present an efficient encryption technique which has low computation complexity. The proposed technique is based on Context-Adaptive Binary Arithmetic Coding (CABAC) where the bin-string of Intra-Prediction Mode, Motion Vector Difference (MVD) and residue coefficients are encrypted with the random behavior of chaotic systems. The random bit streams used for encryption are generated with chaotic systems using Logistic map. The experimental results show that the proposed technique is very effective for real-time applications and robust against different types of attacks.

Low complexity mode selection for H.266/VVC intra coding

H.264/AVC the latest international video coding standard achieves higher compression efficiency than previous video coding standards such as MPEG-4 and H.263. However, this performance gain comes at the cost of an increased computational complexity. To achieve a high coding efficiency, H.264/AVC employs complex mode decision techniques based on Rate Distortion Optimization, the computational complexity is very high[1]. This is a major bottleneck for the H.264/AVC in real-time application. Inter-frame prediction coding is a more important part in H.264/AVC. In order to reduce the computational complexity, a fast mode decision algorithm is proposed for Inter-frame in H.264/AVC video coding standard in this paper. With the new algorithm, the amount of computation involved in the motion estimation and mode decision can be substantially reduced. Simulation results show that the proposed algorithm can reduce 56.52% on average of the total encoding time, with a slight increase in bit rate and a negligible PSNR drop.

This paper presents a new lossless data compression method which can be used for the next-generation image and video codec. As an alternative system for CABAC (context adaptive binary arithmetic coder), a new binary coding algorithm is introduced. However, this method can be applicable to any kind of symbols. Efficiency of the codec in terms of compression ratio and computational complexity is introduced. Basic idea behind the proposed method is hiding data reversibly with a location map.

To minimize Rate-Distortion (RD) cost in video coding, RD Optimization (RDO) technique is adopted, which also brings increasingly computational complexity in Motion Estimation (ME), multiple reference selection and mode decision. In this paper, a Gaussian model based adaptive RD cost prediction method is developed to jointly speed up multiple reference selection and inter-mode decision. Besides the ability of achieving good coding efficiency with much reduced computational power, our method is also with two major advantages. First, it can achieve robust performance, including computational complexity reduction and almost intact video quality, with a wide range of video sequences resolutions and even for various scene changes; second, it could be either individually used or combined with the other efficient mode decision algorithms, and in both cases, our method could achieve remarkable performance, which is revealed by exhaustive experimental results.

High-efficiency video coding is the most recent video compression standard. HEVC is designed to decrease the bit rate of video transmission without affecting the video quality. The intra prediction of HEVC features about 35 directional modes. The planar mode and DC modes are included into it. The decision about the most appropriate intra mode within the coding unit of high-efficiency video encoder is a vital component in video coding. The intra mode decision has been a crucial, computationally complex processing step and has a share of 85% in the overall video coding complexity. The optimal mode is selected by rough mode decision (RMD) process from all 35 modes and final decision of partitioning is taken through the rate distortion optimization (RDO) process. The brute force RD cost calculation process consumes a large portion of HEVC encoding complexity. This paper presents analysis of the spread of 35 directional modes over the video frame and the correlation between the homogeneous or non-homogeneous characteristics of video content and the spread of directional modes over the video frame. The proposed method is based on the sum of average gradient evaluated for each of the 35 directional modes which help to reduce the number of candidate modes for rough mode decision and RD cost calculation. The performance of the proposed algorithm is evaluated on three distinct classes of video sequences. The offline classification accuracy of the proposed scheme is measured to be 90%. The exhaustive analysis of mode decision carried out in the proposed method will be subsequently useful for training machine learning algorithm for early decision about coding unit depth and fast prediction of the appropriate intra mode. The early depth decision and reduction in the number of candidate coding units to be passed through iterative RD cost computation will drastically reduce the computation complexity and increase the encoding time of high-efficiency video encoder.