High-temperature reliability of Flip Chip assemblies

Flip chip technology has been developed for more than 30 years and is widely used in the assembly of high-performance devices that require good functionality on substrate space. Compared to traditional wire bonding interconnection, flip chip technology offers tremendous advantages such as eliminating wire bond connections, increasing input/output (I/O) density, and using less space on substrates. With the rapid growth in flip chip technology, the need for assembly services has been developed. The key challenge in flip chip technology development is to improve the reliability of flip chip assembly. To enhance reliability, underfill materials are applied to the gap between die and substrate to provide mechanical support as well as environmental protection to the assembly. Capillary flow underfill material is used to fill the gap and protect the flip chip bumps for better reliability performance for years, but it has the limitations of lower throughput, higher cost and storage. Transfer molded underfill was developed to replace liquid type underfill materials to provide a high productivity process, less expensive materials and reliable performance. This study compares capillary underfill and molded underfill processes. Suggestions for various flip chip package types and performance concerns are then provided.

Increased functionality requirements coupled with progressively reducing package size have necessitated the integration of flip chip packages into various baseband and application processor products in mobile platforms. Such products use flip chip technology using traditional capillary underfill (CUF) process on a strip based package which is subsequently over molded to finish the end-product assembly. The growing pricing pressures and competitive landscape in mobile-packaging has made it imperative for assembly subcontractors to drive the flip chip assembly cost down. To achieve this without compromising product reliability requires a fundamental shift in the way these packages are assembled. Molded underfill (MUF) approach offers such unique solution with promising advantages over CUF; such as lower material cost, higher through put and excellent reliability to meet the overall product needs of today's evolving mobile market; and is discussed in this paper. Capillary Underfill (CUF) has been the cornerstone of today's flip chip technology in both flip chip BGA and flip chip CSP format. Several advancements in CUF materials and dispense technologies made over years has made CUF the underfill technology of choice for various flip chip applications. However as the need for reducing package assembly cost has grown simultaneously; CUF material and underfill process comes under scrutiny due to higher material cost and slow through put process in the flip chip assembly flow. MUF was explored and found to be a viable lower cost alternative for mobile products by virtue of lower material cost and faster throughput due to batch process operation in strip format. The cost benefit is further complemented by the capability of MUF to enable finer spacing between die-to-die and die-to-passives; as well as smaller keep-out zones to enable reduced die-to-package edge clearance or effectively shrink the overall package size than that with CUF. Use of vacuum assisted molding was also found to be capable to fill very small gap between die and substrate of the order of 50um without voiding concerns. This paper outlines the multidisciplinary effort undertaken to design, develop, and qualify flip chip package with MUF technology for mobile application; which was successfully introduced in high volume production with yields and reliability at parity with an equivalent CUF package. MUF material with fine filler size was chosen from a material screening DOE; and was used in series of test vehicles (TVs) with different package configurations including single die and multi-die flip chip CSP packages. Process and material margin studies were conducted to establish process window for MUF technology with eutectic and Pb-free bump assemblies. Finally MUF technology was intercepted on mobile application processor product with fcTFBGA-12×12 mm sq. package and 7.5×7.5 mm2 die towards a successful introduction into high volume production. MUF challenges as well as known-limitations are also described along with future plan. Further studies are being conducted to characterize and qualify MUF on larger die sizes and/or with finer bump pitches and to establish the process and reliability margins of MUF with the same.

Underfill encapsulation has been demonstrated to be necessary to improve the temperature cycle performance of solder joint interconnections and enhance the reliability of flip chip assemblies. An in-depth understanding of underfill materials is a challenge for packaging engineers to develop underfill materials with functional requirements for applications in IC packaging. This paper investigates the material physical properties observed in a bisphenol/amine underfill system using imidazole as the catalyst and silica as the filler. Typical underfill formulations, comprising epoxy resins, hardeners, silica fillers and catalyst were considered. The impact of the material properties on the reliability of flip chip assemblies was discussed. Test vehicles using 16/spl times/7 mm silicon flip chips assembled and encapsulated with different underfill materials on daisy chain PCBs were subjected to a temperature cycling test at -40/spl deg/C air/20 min to 125/spl deg/C air/20 min. It was found that underfills with high adhesion strength, low CTE and high modulus exhibited high reliability in temperature cycling tests.

Compared with classic solder flip chip technologies, the use of isotropic conductive adhesive for bumping and assembling results in a number of advantages such as a simple yet versatile process, lower temperatures and environmental friendliness. The polymer flip chip (PFC/sup TM/) technology requires suitable bond pads. The commonly used aluminum alloys result in unstable contacts for the conductive adhesives and hence there is an urgent need for an additional under-bump metallization for the PFC/sup TM/ technology. KSW Microtec has developed a technology which is based on electroless deposition of palladium. The metallization is executed as a back end process. The bond pads are deposited with a homogeneous and pin-hole free Pd thin film with a thickness of about 1 /spl mu/m without significant reduction of the Al bond pad metallization. The deposited film surface does not require flash gold metallization because of the noble characteristics of palladium. This simplifies the process in comparison to the well known Ni/Au process. The contact resistance between conductive adhesives and palladium metallization are equal to or better than gold/adhesive interconnections. As an example of the versatility of the PFC/sub TM/ technology, products manufactured by KSW Microtec include chip on dycostrate, chip on flex with screen printed polymer tracks, and smart cards. Experiences with the set-up and qualification of PFC/sup TM/ technology at KSW Microtec are also discussed.

A cost-effective Au-solder flip-chip bonding technology working with unique designs of bonding pads and solder resist on organic substrate has been developed. The increasing demand for smaller and lighter system module, and the design requirements for electrical and thermal enhancement drive the deployment of flip chip technologies. Existing flip chip technologies are briefly reviewed and compared; the key design techniques and solder selection to drive the process improvement are explained in details the process improvements include: 1. Excellent void control over underfill resin; 2. Formation of uniform solder humps on the bonding pads of the substrate; 3. Selection of non-lead solder to enhance interconnection reliability. An 5-chip MCM design example is shown for the improvement of bonding time; a test vehicle used for reliability tests is described, the result of reliability tests confirms Au-solder flip chip bonding technique is a sound bonding process.

In the last few years, flip chip technology has been increasingly employed in a variety of applications in the microelectronics industry. Comparing to conventional wirebonding technology, flip chip provides lower profile, faster signal transfer, and higher I/O density. One of the key materials used in flip chip is the underfill encapsulant, which enhances the reliability of the flip chip device by more than an order of magnitude. Currently, underfilling is carried out at the package level, e.g., each chip has to be processed individually after solder reflow. The encapsulant has to be post-cured subsequently off-line. The slow underfilling process becomes a bottleneck in the high volume manufacturing of flip chip. A joint venture program, sponsored by the Advanced Technology Program (ATP), was formed to explore the next paradigm shift in flip chip packaging technology, namely, processing underfill at the wafer level. In this process, the underfill is deposited on the wafer prior to dicing. At the assembly stage, the singulated die is processed as in standard flip chip reflow operations. The main difference is that the pre-coated underfill with built-in flux will cure concurrently with the reflow of the solder, allowing both electrical and structural interconnection to be achieved simultaneously. Therefore, this wafer level underfill process offers much potential in terms of reduced production time and increased throughput. The process will be directly suitable for high volume production using the existing assembly infrastructure, lowering the cost of implementation. In this paper, the technical challenges and the solutions for both materials development and process verification in this program will be discussed.

Redundant cells are added to a memory chip to replace defective cells during IC fabrication to increase overall wafer yields. Compared to other repairing methods, only a small chip area is needed to design laser fuses, moreover, just a few redundant rows or columns can significantly enhance the yields of memory wafers. The laser fuses are hence the most commonly implemented method to increase yields in both DRAM and SRAM IDMs. In conventional memory packages, either TSOP II or FBGA, the memory chips are probed and repaired first, then packaged, burn-in, and final test. Therefore, there is no issue in covering the laser windows on a memory chip after laser repairs since the laser windows are all encapsulated by molding compound. In flip chip technologies or wafer-level packaging, memory ICs are packaging in wafer forms instead of individual dies. Moreover, memory wafers are normally probed and repaired before packaging, therefore, the laser windows are also encapsulated by underfill materials or by molding compound. However, if the conventional chip probing, burn-in, and laser repair can be done after flip chip bumping or wafer-level packaging, the testing steps can be simplified, the testing cost can be greatly reduced, and more wafer yield can be gained. This study primarily focuses on the laser repair after flip chip bumping to explore the feasibility of laser repair through BCB passivation on top of laser fuses and to develop new processes to protect laser fuses during flip chip bumping. Three different conditions are studied, original laser windows with PI passivation opened, laser windows with BCB coated on the top of PI passivation, and laser windows with BCB coating without PI passivation. The laser windows with PI opened, the laser fuses can easily be “burned” with 1.0 μJ of laser energy and the die can successfully be repaired since a fuse is sublimated by the laser beam with its vapor exploded and broken through the covered dielectrics. There are two different thicknesses of coated BCB in laser windows, one is laser windows with BCB coated on the top of PI passivation and the other is laser windows with BCB coating without PI passivation where the thicknesses are 10.69 μm and 7.32 μm, respectively. The results of laser repair are almost identical. Even with the laser repair energy up to 1.8 μJ, the fuse can not be “burned” and its vapor can not explode and break through the dielectrics and the BCB on top, all the more, its vapor will go sidewards and cause cracks along the interfaces of BCB and the dielectrics, in the worst case, causing shorts between the adjacent fuses. From the results of the laser repair, it can easily be concluded that the fuse vapor cannot easily break through the dielectrics with a thick BCB on top, therefore, no further study on the parameters of laser repair through BCB is necessary. The laser repair should be performed without any BCB passivation nor any bumping residual inside the laser windows. Then, how to protect laser fuses inside the laser windows during flip chip bumping processes becomes very crucial. The protection of laser fuses can be done by using appropriate UBM materials during flip chip bumping processes, then after solder ball reflow, the UBM was removed by etching. It has been proven that the dielectrics on top of laser fuses will not be damaged during flip chip bumping processes.

Applicability of no-flow fluxing encapsulants and flip chip technology in volume production was studied. Adhesion of the underfill materials to different solder resists was measured with single lap shear test and the results compared with traditional underfills. No-flow underfiller was dispensed with standard in line dispenser. SnPb-bumped flip chip test structures were pick and placed on FR4 substrates by using standard volume production line. The bump pitch of the test chips was 250 /spl mu/m. Sample boards were also precured in standard production oven and postcured in baking oven. No-flow underfillers showed exceptionally good adhesion to used solder resists. With the no-flow underfillers flip chip proved to be transparent to the current SMA process, however the process window for dispensing and reflowing is relatively narrow.

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.

Packaging technology is currently transition from flip chip technology to three dimensional integrated circuits (3D ICs) to meet the requirements of consumer electronic products. Compared to flip chip technology, the dimension of microbumps in 3D ICs is shrunk by a factor of 10. In this study, the behaviors of thermomigration in Pb-free solders of flip chip and 3D ICs are presented. When the bump height is 100 μm in the flip chip samples, the Sn protrusion was observed at the hot end and voids formation at the cold end. However, when the bump height is reduced to 5.8 μm in the 3D IC samples, no significant microstructural evolution of Sn was found; instead, the dissolution of Ni under-bump metallization at hot end was observed. We propose that discrepancy between flip chip solder joints and 3D IC microbumps is mainly attributed to the effect of back stress and the presence of thicker Ni under-bump metallization in the 3D IC packaging. Moreover, the critical temperature gradient in terms of different bump heights is discussed, showing below which there will be no net effect of thermomigration of Sn.

A variety of flip chip technologies are available today which differ in bumping material, substrate type, pad metallization and joining method. They are found in packages as well as on multichip modules and directly flip chip bonded on the board. Components including flip chip like ball grid arrays and chip size packages are introduced. Flip chip is the most favored assembly technology for high frequency applications due to the small parasitic of the short bump interconnect. High performance packages for optoelectronic devices using self-alignment during a fluxless reflow soldering are shown as well as the integration of MMICs. High density multichip modules have been fabricated for large pixel detectors of a nuclear detector with eight Chips and more than 46000 I/Os with an acceptable yield. Flip chip technology is a very flexible assembly method for different applications. Variations of the bump structure can be used for MEMS packaging as well and it was demonstrated by the assembly of a thin membrane to form an absolute pressure sensor with a vacuum enclosure. For different packaging requirements the appropriate technology should be chosen very carefully. An overview will be given for different bumping and flip chip joining methods suitable for high volume production as well as for prototyping. Wafer bumping methods will focus on electroless deposition of nickel/gold as well as on electroplating of gold, SnPb and AuSn solders. For rapid prototyping single chip bumping methods are described. Examples of different joining methods - soldering, adhesive bonding and thermocompression bonding - will be shown.

Rework of flip chip bonded radiation pixel detectors

Conductive polymer bonded flip chip interconnect systems can provide an attractive alternative flip chip technology in terms of cost and manufacturability. This work examines the feasibility of application of such a technology. A mathematical model for stencil printing of conductive adhesive paste is developed to demonstrate some of the factors affecting the print quality. Designed experiments is used to optimize bump dimensional uniformity. The electrical performance of conductive polymer flip chip interconnects is evaluated through both GaAs and Si devices. The microwave insertion loss (S/sub 21/) of a coplanar waveguide test vehicle showed a loss rate of 0.031 dB/GHz for non-underfilled flip chip assembly and 0.065 dB/GHz for those with underfill encapsulation. These S/sub 21/ data are almost identical to a device with same test structure and a Au ball bumped flip chip assembly. Additional test using a CT-2 antenna switch GaAs device flip chip bonded on a FR4 board showed an identical performance (up to 2 GHz frequency) to the same assembly using Au-Sn eutectic bumps. Reliability of conductive polymer bumps was evaluated using Si die flip chip bonded on FR4 substrates. Results showed no failures on temperature cycle, humidity, vibration, and mechanical shock tests. There were 8.6% failures on HAST and 6% failures on thermal shock tests on test conditions stated in the text.

This paper demonstrates a combined approach of numerical analysis and experimental investigations to study the mechanical reliability of flip chip solder joints. The effect of various design parameters like bump geometry, soft and hard underfill, and used solder mask on the thermal fatigue life of solder joints is discussed. Since special attention has been directed towards Flip Chip on Board (FCOB) assemblies, constitutive properties of polymeric and solder materials are discussed in detail. The solder is modeled using a nonlinear constitutive law with time dependent (creep) and time independent plastic strains. Furthermore, material testing shows that the underfill and solder mask materials might be considered as linear viscoelastic with temperature time shift properties. Thermal mismatch between the materials assembled is often the main reason for thermally induced stresses. Thermal cycling (125/spl deg/C...-55/spl deg/C...125/spl deg/C) is therefore the load generally used in the 3D non-linear finite element analysis. Calculation results of the solder bump deformation due to temperature changes are accompanied by experimental deformation analysis. The used MicroDAC method is based on algorithms of local object tracking in images obtained from electron scanning microscopy. The measured deformation fields were utilized for proper materials selection and processing, as well as for verification of finite element analysis.

Electronic assemblies are approximately free near their assembly temperature, which is typically above 150 degC when encapsulants and solders are involved. As the assemblies are cooled below room temperature, the temperature difference between ambient and free conditions becomes extremely high, and the thermal expansion mismatch induced stresses, strains, and deformations in the assembly can become very large. This phenomenon is exacerbated by the changes in material behavior that occur at extreme low temperatures present in proposed NASA lunar and Mars missions. In particular, encapsulants become much more stiff/brittle losing their typical nonlinear/inelastic stress-strain characteristics and high strains to failure, and the yield stresses for solders become very high. In this work, we evaluated the mechanical performance and reliability of flip chip on laminate assemblies subjected to extreme low temperatures. Stress measurements have been made in the flip chip assemblies during thermal cycling using stress test chips incorporating piezoresistive sensor rosettes. The (111) silicon test chips were 5 times 5 mm in size, with perimeter solder balls on a 200-micron pitch. The obtained stress measurement data correlated well with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solder, underfill encapsulant, and PCB from -180 to +150 C to aid in the numerical simulations