Underfill material requirements for reliable flip chip assemblies

Flip chip technology has been developed for more than 30 years and is widely used in the assembly of high-performance devices that require good functionality on substrate space. Compared to traditional wire bonding interconnection, flip chip technology offers tremendous advantages such as eliminating wire bond connections, increasing input/output (I/O) density, and using less space on substrates. With the rapid growth in flip chip technology, the need for assembly services has been developed. The key challenge in flip chip technology development is to improve the reliability of flip chip assembly. To enhance reliability, underfill materials are applied to the gap between die and substrate to provide mechanical support as well as environmental protection to the assembly. Capillary flow underfill material is used to fill the gap and protect the flip chip bumps for better reliability performance for years, but it has the limitations of lower throughput, higher cost and storage. Transfer molded underfill was developed to replace liquid type underfill materials to provide a high productivity process, less expensive materials and reliable performance. This study compares capillary underfill and molded underfill processes. Suggestions for various flip chip package types and performance concerns are then provided.

High-temperature reliability of Flip Chip assemblies

No-flow underfill technology has been proven to have potential advantages over the conventional underfill technology. However, due to the filler entrapment between solder bump and contact pad on board, no-flow underfills are mostly unfilled or filled with very low filler loading. The high coefficient of thermal expansion (CTE) of the polymer material has significantly lowered the reliability of flip chip assembly using no-flow underfill, and has limited its application to large chip assemblies. This paper presents a novel approach to incorporate silica filler into no-flow underfill. Two layers of underfills are applied on to the substrate before chip placement. The bottom underfill layer facing the substrate is fluxed and unfilled; the upper layer facing the chip is filled with 65 wt% silica fillers. The total filler loading of the mixture is estimated to be around 55 wt% using Thermo-Gravimetric Analyzer (TGA). The material properties of each layer of underfills and the underfill mixtures are characterized using Differential Scanning Calorimeter (DCS), Thermo-Mechanical Analyzer (TMA), Dynamic Mechanical Analyzer (DMA), and stress rheometer. FB250 daisy-chained test chips are assembled on FR-4 boards using the novel approach. A 100% yield of solder interconnect is achieved with filled no-flow underfill for the first time. Wetting of the eutectic SnPb solder to contact pad on the board is confirmed by Scanning Electronic Microscopy (SEM) and optical microscopic observation. An US patent is filed for this invention. The failure in normal no-flow underfill. Assembly with silica filler is investigated. Other variations of this process are discussed.

Electronic assemblies are approximately free near their assembly temperature, which is typically above 150 degC when encapsulants and solders are involved. As the assemblies are cooled below room temperature, the temperature difference between ambient and free conditions becomes extremely high, and the thermal expansion mismatch induced stresses, strains, and deformations in the assembly can become very large. This phenomenon is exacerbated by the changes in material behavior that occur at extreme low temperatures present in proposed NASA lunar and Mars missions. In particular, encapsulants become much more stiff/brittle losing their typical nonlinear/inelastic stress-strain characteristics and high strains to failure, and the yield stresses for solders become very high. In this work, we evaluated the mechanical performance and reliability of flip chip on laminate assemblies subjected to extreme low temperatures. Stress measurements have been made in the flip chip assemblies during thermal cycling using stress test chips incorporating piezoresistive sensor rosettes. The (111) silicon test chips were 5 times 5 mm in size, with perimeter solder balls on a 200-micron pitch. The obtained stress measurement data correlated well with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solder, underfill encapsulant, and PCB from -180 to +150 C to aid in the numerical simulations

Underfill materials play a key role in the reliability of flip-chip assemblies on organic circuit boards. Underfill selection has great impact on the interfacial integrity, stresses in the die, and strains in the solder bump. Therefore, it is critical to optimize underfill properties for enhanced reliability of flip-chip assemblies. In this study, effect of underfill properties on interfacial integrity, stresses in the die, and strains in solder bumps is investigated using analytical and experimental methods. Interfacial fracture toughness for die/underfill and underfill/circuit board interfaces are obtained using four-point-bend specimens. Effect of underfill properties on die cracking is investigated by an analytical solution for a three-layered structure. The impact of underfill properties on maximum strains in solder joints and their implications on solder fatigue are evaluated using the moire interferometry method. Results show that a good underfill can be characterized as (a) having adequate interfacial fracture toughness at chip/underfill and underfill/circuit board interfaces, (b) minimizing strains in solder bumps, (c) not causing excessive tensile stress in the die, and (d) having fracture toughness higher or comparable to that of the interfaces. In addition to the above essential requirements, underfill should have a high glass transition temperature, good flow properties, and high moisture resistance.

This paper demonstrates a combined approach of numerical analysis and experimental investigations to study the mechanical reliability of flip chip solder joints. The effect of various design parameters like bump geometry, soft and hard underfill, and used solder mask on the thermal fatigue life of solder joints is discussed. Since special attention has been directed towards Flip Chip on Board (FCOB) assemblies, constitutive properties of polymeric and solder materials are discussed in detail. The solder is modeled using a nonlinear constitutive law with time dependent (creep) and time independent plastic strains. Furthermore, material testing shows that the underfill and solder mask materials might be considered as linear viscoelastic with temperature time shift properties. Thermal mismatch between the materials assembled is often the main reason for thermally induced stresses. Thermal cycling (125/spl deg/C...-55/spl deg/C...125/spl deg/C) is therefore the load generally used in the 3D non-linear finite element analysis. Calculation results of the solder bump deformation due to temperature changes are accompanied by experimental deformation analysis. The used MicroDAC method is based on algorithms of local object tracking in images obtained from electron scanning microscopy. The measured deformation fields were utilized for proper materials selection and processing, as well as for verification of finite element analysis.

Conductive polymer bonded flip chip interconnect systems can provide an attractive alternative flip chip technology in terms of cost and manufacturability. This work examines the feasibility of application of such a technology. A mathematical model for stencil printing of conductive adhesive paste is developed to demonstrate some of the factors affecting the print quality. Designed experiments is used to optimize bump dimensional uniformity. The electrical performance of conductive polymer flip chip interconnects is evaluated through both GaAs and Si devices. The microwave insertion loss (S/sub 21/) of a coplanar waveguide test vehicle showed a loss rate of 0.031 dB/GHz for non-underfilled flip chip assembly and 0.065 dB/GHz for those with underfill encapsulation. These S/sub 21/ data are almost identical to a device with same test structure and a Au ball bumped flip chip assembly. Additional test using a CT-2 antenna switch GaAs device flip chip bonded on a FR4 board showed an identical performance (up to 2 GHz frequency) to the same assembly using Au-Sn eutectic bumps. Reliability of conductive polymer bumps was evaluated using Si die flip chip bonded on FR4 substrates. Results showed no failures on temperature cycle, humidity, vibration, and mechanical shock tests. There were 8.6% failures on HAST and 6% failures on thermal shock tests on test conditions stated in the text.

In order to investigate the failure mechanism of microjoints within a chip stacking architecture, four chips with more than 3000 microbumps each were assembled on a Si interposer by Toray's FC-3000WS bonder at a peak temperature of 280°C without any flux. The defects such as missing bumps and deformation of microjoints induced by the undercut of Cu pillar have been improved based on a new design rule of seed layer. Then two different underfill materials were used to seal the microgaps between the chips and the interposer, respectively. They were post-cured at 150°C for 30 minutes and 165°C for 120 minutes. The inspection results of scanning acoustic microscope (SAM) showed that no gas voids were formed within the underfill material having a lower viscosity of 9 Pas and a smaller averaged filler size of 0.3 um, even though the gap width is less than 20 μm. In the previous works [7, 8], the authors pointed out that the 30 μm pitch microjoints are easily failed under temperature cycling test (TCT), therefore, the same test condition (JESD22-A104-B, Condition B, Soak mode 2) were adopted again to assess the reliability of the 20 um pitch microjoints sealed by different underfill materials. From the test results, the various underfill materials gave different failure rates but had the same failure mode under TCT, and the microjoints sealed by the previously mentioned underfill had a longer lifespan. The cross-sectional images of scanning electronic microscope (SEM) indicated that the failure was induced by the interfacial fracture of the microjoints. The elemental distributions of Sn and Ni were identified by mapping analyses using energy dispersive spectrometer (EDS), in which the intermetallic phase of Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> at the chip-side and the interposer-side could not cohere during their growth as heated. This is because a Sn depletion zone caused by the unbalanced growth kinetics of the Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> at both interfaces was formed in the microbumps at the chip-side as aged, and which perhaps made the Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> have too much defects and could not link up with the Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> at the interposer-side by solid-solid interdiffusion. Finally, the tensile stress came from the thermal expansion of underfill resulted in the fracture of the 20 μm pitch microjoints along the interface between the Ni layer and the Sn2.5Ag solder alloy of the top chip.

S.21-30

The characteristics of underfills and flip chip packaging have been studied at length over the past few years. The correlation of the underfill and the assembly process, however, is key in ensuring a high performance flip chip package. Thus, the changes in the behaviour or characteristics of the material must be identified as the process changes. The assembly process itself may sometimes be the cause for package failure, as it could have caused the material to change in behavior or even be destroyed. A recent study has looked at the flow characteristics and the matching of the underfill material and the substrate or die. This study of a cyanate ester based underfill material focuses specifically at the adhesion strength of the material as it proceeds through the flip chip packaging assembly process. The assembly process includes underfill cure, encapsulation material cure followed by preconditioning and IR reflow. An epoxy based underfill material is used as control to compare the performance of the cyanate ester based material. Additional information such as modulus, weight loss and warpage are also presented. From the results obtained, it is clear that the initial performance of the underfill material after cure is not a good indicator of its actual performance after flip chip assembly. Some key parameters such as outgassing and moisture absorption are also deduced from the results.

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.

The use of anisotropically conductive adhesives (ACAs) for the direct interconnection of silicon chips to printed circuits offers numerous advantages including: reduced package thickness, improved environmental compatibility, lowered assembly temperatures, increased metallization options, and decreased equipment needs. To increase throughput and to lower costs, we have developed a new approach to flip-chip assembly with ACAs. Our process uses two unique features: an ACA thixotropic paste formulation and a batch curing fixture. The thixotropic paste, which replaces the more conventional film form of the adhesive, can be easily dispensed onto the substrate with a stencil printer. Chips placed into the ACA paste are held securely due to the tacky nature of the material much like surface mount components are held by solder pastes. As a result, no heating of the chips is required during assembly, increasing throughput and relaxing co-planarity tolerances in the alignment equipment. As with all ACAs, the paste must be cured by the simultaneous application of heat and pressure. In our process, curing is accomplished in a fixture capable of holding multiple chips and/or circuit boards simultaneously. Uniform pressure is applied to components during the 3-5 minute thermal cure cycle via a conformable silicone rubber bladder. Initial yield and temperature cycling data are reported in this paper. Silicon chips with gold metallization show small (<15%) increases in contact resistance after more than 1000 test cycles (between 0-100/spl deg/C); bumping the chips was not required. Aluminum metallized chips proved to be unreliable after temperature cycling tests.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Continued standards in reliability and shorter time to market have resulted in an increased focus on reliability modeling and correlation to shorten robust device development. One of the most time consuming and mechanically stressful reliability tests to qualify a product is Temperature Cycling (TC). In plastic packages with exposed pads to be connected to a printed circuit board, a common failure mode in TC test is die pad delamination due to coefficient of thermal expansion mismatches within the package. Thermal Shock (TS) reliability test is similar to TC with the advantage of being much faster to execute. In this study, die pad delamination is correlated for TS and TC using three test vehicles. A scanning acoustic microscopy based delamination extraction approach is described, and a Finite Element Analysis is used to develop a predictive TC thermo-mechanical model.