Flip-chip assembly and reliability using gold/tin solder bumps

RDL (Re-Distribution Layer) structure is an interim product to link up IC chip for wire bonding and flip chip assembly. We can perform area array solder bumps on a chip with peripheral IC pads by means of RDL rerouting technology, and the re-design and re-fabrication procedures of IC chip will not be required. The flip chip technology not only offers miniaturized packaging and higher I/O count but also has better electrical, thermal and reliability performances in comparison with traditional wire bonding. In this study, we investigate how to enhance the reliability property of solder bump with RDL structure by means of materials utilization, bump design and process optimization. In Chapter 1, how WLCSP works and its benefits will be described. Under traditional gold wire design , the I/O pad of IC with peripheral pad turn to area array by RDL rerouting technology. In Chapter 2, the issues faces under RDL process re mentioned, including di-electric de-lamination due to bad adhesion, howthe adhesion improved, and the comparions between different bump structure, with various de-electric selection. Chapter 3 illustrates experiment design, Chapter 4 discusses the testing results from those samples which pass Reliability test , and result in raise Reliability of RDL technology . The end product of this thesis is a WLCSP package composed of bare die onto FR4 substrate without underfill. The optimal design of RDL structure in the study has been qualified and passed wafer-level and board-level reliability tests, including temperature cycling test for 1000 cycles from -55C to 125C

To achieve good reliability and high performance flip chip interconnection, process parameters and materials used in the flip chip process must be optimised. In this paper reliability of Sn37Pb solder bumped flip chips on an FR5 board, using different fluxes and underfill materials, are tested in a temperature cycling test. Also the contact pad geometry used on the FR5 board had a great influence on the reliability of the joint. The solder bumps were grown on the well‐known TiW/Au under bump metallurgy (UBM1) with an extra layer of nickel (UBM2) which gives a reliable and high performance solder joint.

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance.

Conductive polymer bonded flip chip interconnect systems can provide an attractive alternative flip chip technology in terms of cost and manufacturability. This work examines the feasibility of application of such a technology. A mathematical model for stencil printing of conductive adhesive paste is developed to demonstrate some of the factors affecting the print quality. Designed experiments is used to optimize bump dimensional uniformity. The electrical performance of conductive polymer flip chip interconnects is evaluated through both GaAs and Si devices. The microwave insertion loss (S/sub 21/) of a coplanar waveguide test vehicle showed a loss rate of 0.031 dB/GHz for non-underfilled flip chip assembly and 0.065 dB/GHz for those with underfill encapsulation. These S/sub 21/ data are almost identical to a device with same test structure and a Au ball bumped flip chip assembly. Additional test using a CT-2 antenna switch GaAs device flip chip bonded on a FR4 board showed an identical performance (up to 2 GHz frequency) to the same assembly using Au-Sn eutectic bumps. Reliability of conductive polymer bumps was evaluated using Si die flip chip bonded on FR4 substrates. Results showed no failures on temperature cycle, humidity, vibration, and mechanical shock tests. There were 8.6% failures on HAST and 6% failures on thermal shock tests on test conditions stated in the text.

Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic solder with underfill. Several types of ACF and ACP with different types of conductive particles and adhesives were investigated. Simple but high yield procedures for reworking flip chip on board using ACP and ACF were developed. Processes for flip chip on FR‐4 and ceramic boards using eutectic solder bumps with underfill were also evaluated. The flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the three processes (gold bumps with ACF, gold bumps with ACP, and eutectic solder bumps with underfill) is compared.

Flip chip technology offers a number of advantages over conventional packaging techniques such as smaller size and efficient high-speed signal transmission. However, when assembled on organic substrates, the flip chip needs to be underfilled with a suitable adhesive to enhance the thermo-mechanical reliability of its solder bumps. When such flip chip assemblies are subjected to thermal excursions, the underfill material may delaminate resulting in premature solder bump fatigue failure. Available open literature has extensively focused on underfill delamination propagation due to monotonic loading conditions. However, the information on underfill fatigue delamination propagation is limited. This paper presents an experimental and modeling study on the underfill delamination under monotonic as well as fatigue loading conditions. In this work, the fracture toughness of the passivation-underfill interface has been characterized using the single leg bending test. In addition, a fatigue delamination propagation experiment has been done, and a Paris law type model for delamination propagation has been developed. In parallel, numerical models have been developed to determine the available energy release rate under monotonic loading conditions as well as the range of energy release rate range under thermal cycling conditions. The mode mixity calculations have been carried out using Crack Surface Displacement (CSD) method. Using the models and the experimental data, guidelines against the delamination of the underfill material are developed.

Underfill encapsulation has been demonstrated to be necessary to improve the temperature cycle performance of solder joint interconnections and enhance the reliability of flip chip assemblies. An in-depth understanding of underfill materials is a challenge for packaging engineers to develop underfill materials with functional requirements for applications in IC packaging. This paper investigates the material physical properties observed in a bisphenol/amine underfill system using imidazole as the catalyst and silica as the filler. Typical underfill formulations, comprising epoxy resins, hardeners, silica fillers and catalyst were considered. The impact of the material properties on the reliability of flip chip assemblies was discussed. Test vehicles using 16/spl times/7 mm silicon flip chips assembled and encapsulated with different underfill materials on daisy chain PCBs were subjected to a temperature cycling test at -40/spl deg/C air/20 min to 125/spl deg/C air/20 min. It was found that underfills with high adhesion strength, low CTE and high modulus exhibited high reliability in temperature cycling tests.

This paper presents and discusses experimental results which successfully demonstrate using flip-chip techniques, the bonding and operation of a GaAs edge emitting laser on a silicon substrate having recessed bonding pads. The flip chip alignment and bonding technique is discussed first, focusing on experimental results for both flux and flux-less forms of solder bump processing, the developed flux-less technique is shown to provide comparable solder bump integrity and yield. Subsequent to the newly developed solder bump fabrication methodology shown, a recessed bonding pad design is introduced and demonstrated experimentally to aid in the final coarse alignment and assembly of the GaAs laser device onto a silicon substrate. Together both the flux-less solder bump and bonding pad recess design and fabrication processes provide increased reliability for integration with MEMS and MOEMS based devices and systems over traditional methods for hybrid device attachment.

In this study, solder bump flip chip assembly using NCFs was evaluated for Sn-Ag solder bumps. Flip chip bonding was performed using an isothermal Thermo-Compression (TC) bonding method for 5 seconds. Solder bump joints were evaluated by adjusting the curing properties such as curing onset, peak temperature, and degree of curing and viscosities of NCFs using curing agents and silica contents. And then, the degree of cure and viscosity approximations were conducted to define the precise viscosity of NCFs at the solder melting temperature using measured degree of cures at various bonding temperatures and viscosities. Finally, high temperature and humidity test (85RH%/85°C test) and temperature cycling (T/C) test were performed to evaluate the thermo-mechanical reliability performance depending on solder joint.

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and throughput. As an alternative, a solder bump inspection system is being developed at Georgia Tech using laser ultrasound and interferometric techniques [1]. This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the surface of the chip or packages using laser interferometric technique. This paper presents a systematic study on thermo-mechanical reliability of flip chip solder bumps using laser ultrasound-interferometric inspection system and finite element (FE) simulation. The correlation between the failure parameter of solder bumps extracted from FE simulation and the quality degradation results of solder bumps from laser ultrasound testing has also been studied. Accelerated thermal cycling (ATC) tests were performed in two phases on flip chip package (FCP) test vehicles with 63Sn37Pb solder bumps. In phase I, four boards were thermal cycled up to 70 cycles. Every ten cycles, the boards were taken out and FCPs on each board were tested for presence of cracks using resistance and laser ultrasound testing methods. These measurements were repeated every 10 cycles and stopped after 70 cycles. Laser ultrasound testing results show that beginning from 10 cycles, testing values began to increase gradually until 50 cycles when there was a sharp jump (through crack verified at 50 cycles with cross-section). Cross-section was done only after 70 cycles, and the results show that solder bumps at the corners had through cracks, while solder bumps at the center had partial cracks. Phase II studies were refinements of phase I studies. In phase II studies, seven boards were thermal cycled starting from 27 cycles to 56 cycles at an increment of approximate five cycles. After every five cycles, only one board was pulled out and tested in order to track crack initialization and propagation in solder bumps. Smaller thermal cycle increments were used to help determine exactly when cracks initiated and propagated. It was shown that laser ultrasound technique could track solder bump crack propagation induced by thermal cycling. The elastic-plastic-creep and Anand's viscoplastic constitutive models have been used in FE simulation to describe the inelastic deformation behavior of solder bumps. A three-dimension FE model was implemented using ANSYSreg on the same FCP as used in the ATC testing. The stress-strain results were extracted from FE modeling and the inelastic strain energy density (SED) per cycle calculated at the critical solder bump position was used as a failure parameter. It was found that there was a good correlation between inelastic SED extracted from FE simulation and results from laser ultrasound testing.

An assembly process for environmentally conscious low cost flip chip assembly to microvia laminate substrates is presented, based on a fully integrated high speed flip chip assembly line. The process includes the flux application, chip placement, reflow process, and underfill processing. Flux and underfill material compatibility is discussed, and data presented analyzing the quality of the solder joint formation and underfill adhesion to halogen-free solder masks. 204-/spl mu/m pitch peripheral bump, daisy chain test chips with edge lengths of 5 mm and 10 mm respectively are used. Comprehensive reliability results, are presented, comparing the two lead-free to tin/lead eutectic interconnect systems. The chips are assembled on microvia substrates with electroless nickel/immersion gold surface finish, comparing conventional to halogen-free FR-4 and solder masks. A fast flow snap cure underfill, qualified for use with eutectic tin/lead joints on conventional FR-4, is used for both board types. Reliability results from air-to-air thermal shock testing are presented, comparing lead-free to eutectic interconnect systems mounted on conventional and halogen-free microvia substrates. Process and failure mode analysis are presented, based on X-ray inspection, C-SAM analysis, and assembly cross sections.

Increased functionality requirements coupled with progressively reducing package size have necessitated the integration of flip chip packages into various baseband and application processor products in mobile platforms. Such products use flip chip technology using traditional capillary underfill (CUF) process on a strip based package which is subsequently over molded to finish the end-product assembly. The growing pricing pressures and competitive landscape in mobile-packaging has made it imperative for assembly subcontractors to drive the flip chip assembly cost down. To achieve this without compromising product reliability requires a fundamental shift in the way these packages are assembled. Molded underfill (MUF) approach offers such unique solution with promising advantages over CUF; such as lower material cost, higher through put and excellent reliability to meet the overall product needs of today's evolving mobile market; and is discussed in this paper. Capillary Underfill (CUF) has been the cornerstone of today's flip chip technology in both flip chip BGA and flip chip CSP format. Several advancements in CUF materials and dispense technologies made over years has made CUF the underfill technology of choice for various flip chip applications. However as the need for reducing package assembly cost has grown simultaneously; CUF material and underfill process comes under scrutiny due to higher material cost and slow through put process in the flip chip assembly flow. MUF was explored and found to be a viable lower cost alternative for mobile products by virtue of lower material cost and faster throughput due to batch process operation in strip format. The cost benefit is further complemented by the capability of MUF to enable finer spacing between die-to-die and die-to-passives; as well as smaller keep-out zones to enable reduced die-to-package edge clearance or effectively shrink the overall package size than that with CUF. Use of vacuum assisted molding was also found to be capable to fill very small gap between die and substrate of the order of 50um without voiding concerns. This paper outlines the multidisciplinary effort undertaken to design, develop, and qualify flip chip package with MUF technology for mobile application; which was successfully introduced in high volume production with yields and reliability at parity with an equivalent CUF package. MUF material with fine filler size was chosen from a material screening DOE; and was used in series of test vehicles (TVs) with different package configurations including single die and multi-die flip chip CSP packages. Process and material margin studies were conducted to establish process window for MUF technology with eutectic and Pb-free bump assemblies. Finally MUF technology was intercepted on mobile application processor product with fcTFBGA-12×12 mm sq. package and 7.5×7.5 mm2 die towards a successful introduction into high volume production. MUF challenges as well as known-limitations are also described along with future plan. Further studies are being conducted to characterize and qualify MUF on larger die sizes and/or with finer bump pitches and to establish the process and reliability margins of MUF with the same.

This paper describes a study of the effects of a delamination at the silicon/underfill interface on the fatigue life of the solder joints of a flip chip. It was first shown that it is important to consider creep deformation during the ramp times, in order to capture the deformation of the solder joints correctly. The effect of the size and location of typical delaminations in a flip chip assembly was then studied. A total of seven cases were simulated using three-dimensional finite element models. These consist of a baseline case with no delamination, and six other cases with different delamination sizes and locations. The fatigue life of the most critical solder joint was found to vary nonlinearly with delamination size and exponentially with distance between delamination and solder joint. It has been established in the literature that the most critical solder joint in a flip chip assembly is the outermost one. However, it was found in this study that the presence of a delamination near another solder joint can cause that particular solder joint to become the most critical one in the flip chip assembly.