Reliability of flip chip components soldered on FR5 board

When a bare die is flipped directly onto the printed circuit board (PCB) during chip-on-board assembly, it becomes exposed to a number of factors, which could influence its electrical performance. Although the mechanical integrity of flip-chip devices has been thoroughly studied, there is very little evidence of detailed investigations of the electrical performance of these devices. The present paper aims to bridge this gap by studying the electrical parameters of flip chip devices and analysing the changes occurring following assembly. A dedicated test chip comprised of passive and active semiconductor devices was designed for the study. Two different types of tacky flux and underfill materials were used in the flip chip assembly process. The flip chip structures were then subjected to various environmental stress techniques for accelerating ageing. Electrical parameters of the devices such as threshold voltage, I-V characteristics, off-state leakage current, current gain, and resistance were measured at various stages of the programme. A slight change in device parameters was observed immediately after assembly. Further change in some device parameters was observed after environmental stressing. The paper investigates the mechanisms that could be responsible for the changes, such as mechanical stresses introduced during the flip chip process or ionic contamination inherent to the assembly process.

In this paper, the root cause and solution of bump deformation failure of memory product in FC(Flip chip) process were studied through experimental and simulation method. After analysis, MUF (Mold under fill) unbalanced flow was proposed to be the real root cause for this type of failure. In order to verificate it, the simulation method was proposed to explain what level of stress did the bump suffer during the mold process. What' more, It was found that all the kinds of products with bump deformation have a larger size of die than those products without bump deformation. So the simulation method was proposed to simulate the MUF flow by different size of die. In order to solve the bump deformation problem, the mold process was optimized. The key parameter which effects the bump deformation was found by DOE. Then the profile was optimized and the result showed that it avoided the bump deformation failure a lot.

Motorola's implementation of a high volume low cost flip chip assembly process required IC bumping operations, printed circuit board design, and manufacturing issues to be addressed. The electroplated bumps were eutectic tin/lead with a copper stud under bump metallurgy (UBM) customized to 45 microns. The copper stud maintains the post-reflow silicon to printed circuit board standoff. Careful attention to detail was maintained during the printed circuit board design. FR-4 with an electroless nickel/gold surface finish was the substrate of choice due to its low cost relative to BT and HDI. The PCB layout had to adhere to design rules acceptable to high volume low technology PCB houses. Consequently, the limitations of the circuit board fabricators determined the silicon redistribution, bump pitch, bump size, and the placement equipment requirements. Incorporating flip chip assembly into an existing SMT production line posed significant challenges to the factory. Fluxing, die placement, underfill and cure operations required characterization prior to production ramp up. Manufacturing process windows were defined and implemented to avoid potentially expensive flip chip yield losses due to skewed die, opens, shorts etc. The use of innovative fabrication and design techniques has allowed Motorola to successfully ship several million pagers incorporating a low cost flip chip assembly. In addition to providing a substantial contribution to Motorola's bottom line, the flip chip process has demonstrated excellent assembly yields and field reliability.

The flip chip, a type of chip mounting used in semiconductor devices, has become one of the most popular innovations in the semiconductor packaging industry. The height of flip-chip solder bumps ranges from 20 to 140 mum with a required measurement accuracy of 2 mu m. Three-dimensional (3-D) measurement of flip-chip solder bumps is crucial to flip-chip manufacturing quality and process control. Currently, 3-D measurement systems for flip-chip solder bumps are mainly based on laser scanning techniques. However, they require a high implementation cost, and suffer from low inspection speed due to the physical line-scanning process. In this paper, a fast and cost-effective 3-D measurement system for flip-chip solder bumps is proposed. The proposed system is based on a phase shift technique, in which the phase is accurately shifted by a software-controlled grating using a digital light processing (DLP) unit that allows full-field measurement of a projected flip chip. The DLP unit can provide a higher fringe-contrast pattern at a faster changing time than a liquid crystal display (LCD) panel. Phase shift-based measurement systems require a calibrated system parameter, which is generally considered a fixed value in currently available methods. In this paper, adaptive parameter values, instead of a fixed value, are used to improve measurement accuracy. The proposed system also adopts a fringe-contrast thresholding to solve the pseudo-surface height problem for high reflective solder bumps and low reflective substrate in a flip chip. Experiments have shown that the 3-D measurement of flip-chip solder bumps is very efficient and effective with the proposed system. Computation time of the proposed 3-D measurement system for a 640 x 480 image that contains almost 500 solder bumps is less than 1 s, and measurement accuracy meets the required specification of 2 mum.

Experiences in flip chip production of radiation detectors

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Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance.

Flip chip has become the preferred package solution for high performance IC and microprocessor device [1]. In the area of flip chip, advanced Si node is always the mainstream technology. The integration of highly fragile ELK inner layer dielectric (ILD) material plays an important role to reduce the circuit delay time. In addition, the increasing performance demand continues to drive the scaling of feature size of the silicon as well as tighter bump pitch, smaller bump diameter and large die size for future flip chip packages [2]. From the last decade, there has been a significant focus on the development of Pb-free bump interconnection in flip chip package [3]. The Pb-free bump interconnection leads to significant challenges because the elastic modulus and yield strength of Pb-free alloys are significantly higher than that of conventional eutectic Sn-Pb material, and higher melting temperature is required to meet the Pb-free soldering in chip attach process. As a result, ILD delamination has emerged as a major reliability concern with the adoption of the intrinsically higher stiffuess of Pb-free solder and lower mechanical strength of ELK dielectric materials in silicon backend structure. It is a challenge to manufacture a robust and reliable advanced flip chip product [4-6]. In this paper, we summarize some of the early development work of the high performance ASIC. The die size of the test vehicle is approximately 18x19mm fabricated using 40nm ELK technology incorporating Sn-1.8Ag plated bumps whose pitch is 150um (minimum). It is fabricated on 300mm wafer with polyimide passivation. The laminate is a 50x50mm square substrate with 800um core and 5-2-5 (12 layers) build-up structure. The Pb-free BGA has 2397 pads with 1.0mm pitch and full array format. It is well known that underfill materials and related processes are key technology for flip chip BGA (FCBGA) packaging. Underfill is an epoxy silica composite material with optimum thermo-mechanical properties (CTE, Tg, Modulus) to minimize stress transfer to die, then to prevent solder joint fatigue, ELK ILD delamination and die crack. In this study, UF selection is conducted to compare different underfill materials process capability, compatibility and reliability performance in accelerated stress tests. Common failure modes are studied, e.g., ILD delamination besides UF crack and interfacial delamination between polyimide and UF. One underfill option has passed internal qualification test including uHAST 96hrs, TCB 1000 cycles and HTST 1000hrs.

This paper discusses flip chip on FR‐4 and ceramics using non‐conductive adhesive (NCA), anisotropic conductive film (ACF), or anisotropic conductive paste (ACP). Several ACF and ACP materials with different types of adhesive resin and conductive particles and one NCA material were evaluated. Flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the processes was compared. Flip chip processes using NCA, ACF, or ACP could give satisfactory reliability and high assembly yield for some applications, when the bonding parameters were optimised.

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captured deformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

A new under bump metallurgy (UBM) solution consisting of the TiW‐, Au‐ and Ni‐layers for solder flip chip applications has been developed. The metallurgy, being based on the well‐known TAB metallisation procedure, was modified by producing the galvanic nickel layer on the top of the Au‐TiW metallisation. Nickel is needed between high Sn liquid solder bumps and the Au layer to prevent fast and extensive dissolution of thin Cu or Au layers and consequently excessive intermetallic formation. The flip chip joints were manufactured, employing both the 60Sn40Pb‐ and pure Sn‐bumped chips together with the new UBM, which is relatively easy to implement into volume production. The different ageing tests demonstrated that reliable joints can be produced by using the UBM. On the basis of the results obtained the new UBM was found to be a significant improvement in the production of reliable flip chip joints.

System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever smaller products is continuously pushing development of new materials, components and assembly technologies. An optimization study of a SiP design based on a functional product is discussed in this presentation to address the following: 1. Design optimization to reduce component spacing with varied assembly challenges 2. Substrate stack-up optimization for z-height reduction with coreless substrate technologies 3. Flip chip (FC) bump pad optimization for ball bumped or copper-pillar bumped CMOS silicon's 4. Cost reduction potential to replace SOP with paste printing using u-stencil for flip chip applications 5. Assessment of different MUF and fluxing underfill (FU) materials To accomplish these objectives, two types of bumped silicon wafers/dice, three different substrates and four different materials were implemented in this DOE. Short-looped wafers of an actual live device were bumped with CuP pillar as well as with SnAg ball bumping technologies. All three substrate designs are coreless, as compared with the original POR conventional design. One substrate was designed with the plan-of-record (POR) component spacing on a 6-layer stack-up that results in ∼ 290 um overall z-height; X-Y-Z size reductions were achieved on the alternative 4-layer design that has reduced component spacing as well as a reduced overall z-height of ∼ 190 um; furthermore, embedded trace substrate (ETS) was used as the top layer for the 4-layer designs to ensure improved routing capabilities. Subtle differentiation between these two 4-layer designs is in the die shadow area on the top ETS layer: while one design uses solder mask defined pads (SMD) the other uses the ETS dielectric materials to define the flip chip bonding pads without solder mask (NSMD). The latter design facilitates the MUF flows for ultralow stand-off flip chip solder joints and make it a likely “universal” pad design for both CuP and SnAg flip chip bump attach. Four different MUF materials along with one FU materials were used for DOE assembly: the first MUF is the POR material currently used in HVM production with nominal filler sizes; 2nd MUF is for low warpage applications (especially for thin, coreless substrate); 3rd MUF has a smaller filler size that is optimized for small stand-off flip chip bumps and the last MUF has a much improved thermal conductivity and is assessed here for its fit-for-use in other high thermal density applications. FU used is an underfill material with build-in flux and is opportunistically included here to assess its fit for use for our future products. Overall DOE plans shall be described, preliminary results as well as the screening test plan will be presented in some detail and implication of these interacting factors in improving a SiP design to achieve small form end product will be discussed.

An assembly process for environmentally conscious low cost flip chip assembly to microvia laminate substrates is presented, based on a fully integrated high speed flip chip assembly line. The process includes the flux application, chip placement, reflow process, and underfill processing. Flux and underfill material compatibility is discussed, and data presented analyzing the quality of the solder joint formation and underfill adhesion to halogen-free solder masks. 204-/spl mu/m pitch peripheral bump, daisy chain test chips with edge lengths of 5 mm and 10 mm respectively are used. Comprehensive reliability results, are presented, comparing the two lead-free to tin/lead eutectic interconnect systems. The chips are assembled on microvia substrates with electroless nickel/immersion gold surface finish, comparing conventional to halogen-free FR-4 and solder masks. A fast flow snap cure underfill, qualified for use with eutectic tin/lead joints on conventional FR-4, is used for both board types. Reliability results from air-to-air thermal shock testing are presented, comparing lead-free to eutectic interconnect systems mounted on conventional and halogen-free microvia substrates. Process and failure mode analysis are presented, based on X-ray inspection, C-SAM analysis, and assembly cross sections.

Flip chip technology is one of the fastest growing segments of microelectronics packaging because of its ability to satisfy the increasing demands of high input/output density, package miniaturization, and reduced cost. A critical element in the successful application of flip chip technology is the reliability of solder bumps. In this paper, a nondestructive inspection method combining ultrasonic excitation with modal analysis is proposed for flip-chip solder bump defect detection. The signal generator and power amplifier are utilized to drive the capacitive air-coupled ultrasonic transducer to produce continuous ultrasonic waves for exciting the test chips. The vibration velocities of the chips are measured by the laser scanning vibrometer to extract the modal shapes and resonance frequencies. The results prove that the defective chips can be distinguished from the good chip by the modal shapes, and the resonance frequencies of the chips decrease with the increase of the open solder bumps. Therefore, this detection method may provide a new path for the improvement and innovation of flip chip on-line inspection systems.

This series of articles studies the processing, moisture sensitivity, reliability, and failure mode analysis of a number of commercial fast-flow, snap-cure underfill materials. It includes data on process analysis, processing times, and reliability of the test vehicles in air-to-air thermal cycling (-55/spl deg/C to 125/spl deg/C), liquid to liquid thermal shock (-55/spl deg/C to 125/spl deg/C), and J Standard 020 Revision A Level 3 Moisture Sensitivity Preconditioning followed by reliability testing. Samples cured using a second reflow pass are compared to baseline samples cured in a standard batch oven based on the underfill manufacturer's recommended cure schedule. Results from the processing of these new materials have shown a greatly reduced flow time from earlier generation underfill materials as all of these materials had flow times of less than 30 s under 5-mm test die. Through differential scanning calorimetry analysis, it was shown that materials requiring less than 8 min to cure exhibited at least 95% conversion (percentage of material cured) through the modified second side renew profile. Some of these commercial underfills have also passed J Standard 020 Revision A Level 3 Moisture Sensitivity testing. Specifically in this paper, the flip chip processing, underfill processing, moisture preconditioning, and preconditioning failure modes are presented.