High throughput Farrow re-samplers utilizing reduced complexity FIR filters

Finite-length impulse response (FIR) filters offer several good properties, like guaranteed stability and exact linear phase; however they require a higher filter order to fulfill a given specification as compared to Infinite-length impulse response (IIR) filters, especially when the transition band is relatively narrow. In this paper a model is proposed to design FIR filter by modifying the MLSE (Mean Least Square Error) method. This model brings significant reduction in the order of FIR filter as compared to other methods of FIR filter designing. This obtained FIR filter is insensitive to bit variation in filter coefficient length up to 5-bit. Not only the magnitude response, but also the Group delay response retains its shape for 99.5% of the normalized frequency band.

In the recent few years, it is observed that in wireless communication there has been a rapid growth in terms of different communication standards/ technologies being used. Thus, to support different communication standards, flexible system should be used to convert the digital signal from one sample rate to another (up sampling or down sampling). The solution is the use of Software defined Radio (SDR), which is a reconfigurable radio communication system. Therefore the most critical and demanding element in the digital signal processing chain of an SDR is the Sample Rate Converter. At high sampling rate, the signals cannot be processed by using baseband signal processing unit. Instead of any unique air-interface, SDR simultaneously handles multiple air-interfaces of different wireless standards that require sample rates for baseband processing. Thus, in SDR, Sampling Rate Conversion (SRC) is an important functionality to provide synchronization between the ADC and baseband signal processor. This paper provides a review on various types of SRC circuits, where their design characteristics are analyzed and compared. The review is based on designing of Sample Rate converters on Field-Programmable Gate Array (FPGA) and Applications Specific Integrated Circuit (ASIC) platform. For FPGA based design, LUT, slices, FFT, and other hardware resource parameters are estimated to evaluate their performance. For ASIC, area, power and delay are considered for performance evaluation.

This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in all branches of the Farrow structure. The second case uses linear-phase FIR filters in every second branch. These branches have milder restrictions on the approximation error. Therefore, even with a reduced order, for these linear-phase FIR filters, the approximation error is not affected. However, the arithmetic complexity, in terms of the number of distinct multiplications, is reduced by an average of 30%. Design examples illustrate the method.

This paper considers the design of digital linear-phase finite-length impulse response (FIR) filters that have adjustable bandwidth(s) whereas the phase response is fixed. For this purpose, a structure is employed in which the overall transfer function is a weighted linear combination of fixed subfilters and where the weights are directly determined by the bandwidth(s). Minimax design techniques are introduced which generate globally optimal overall filters in the minimax (Chebyshev) sense over a whole set of filter specifications. The paper also introduces a new structure for bandstop and bandpass filters with individually adjustable upper and lower band edges, and with a substantially lower arithmetic complexity compared to structures that make use of two separate adjustable-bandwidth low-pass and high-pass filters in cascade or in parallel. Design examples are included in the paper.

This paper presents an approach of model-based design for implementing a digital communication system on a field programmable gate array (FPGA) for a software defined radio (SDR). SDR is a popular prototyping platform for wireless communication systems due to its flexibility and utility. A traditional SDR system performs nearly all computations and signal processing tasks on the host computer, and then sends the waveform to the RF front end. For complex algorithms or high data rate, the host computer becomes the processing bottleneck and FPGA is often employed as a hardware accelerator. This paper demonstrates the procedure of using model-based design for SDR targeted on FPGA hardware. A complete digital communication system, including a transmitter with convolutional encoder and a receiver with Viterbi decoder, is implemented on an FPGA-based SDR platform and validated by over-the-air demonstration. Synchronization algorithms, such as carrier frequency offset, phase offset, and time recovery, are also optimized for hardware efficiency.

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

The book focuses on the cost/area, performance and power consumption differences between Field-Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). These differences are referred to as the gap between FPGAs and ASICs and knowledge of this gap is fundamental for people who design FPGAs, who use FPGAs, or who are considering their use. This book reviews and examines the gap in two ways. The first portion of the book focuses on measurements of the silicon area, performance, and power consumption gap. This is done by comparing designs implemented on a commercial FPGA and using an ASIC methodology. Through this comparison, various trends are noted to elucidate some of the design choices that can narrow the gap. The latter half of the book focuses on the trade-offs that can be made in the creation of a FPGA to narrow the gap selectively. This is useful because silicon area, performance and power consumption are not equally important to all users of FPGAs. The book describes the approach used to investigate these trade-offs and it includes a detailed description of the transistor sizing tool developed to assist in this investigation. The scope of the trade-offs is then examined and the effect of these trade-offs on the FPGA to ASIC gap is considered. The idea of making cost and performance trade-offs has been considered in past works but this book explores the use of transistor-sizing to enable these trade-offs.

Design of digital systems for arbitrary sampling rate conversion

This paper proposes a method for designing high-order linear-phase finite-length impulse response (FIR) filters which are required as, e.g., the prototype filters in filter banks (FBs) and transmultiplexers (TMUXs) with a large number of channels. The proposed method uses the Farrow structure to express the polyphase components of the desired filter. Thereby, the only unknown parameters, in the filter design, are the coefficients of the Farrow subfilters. The number of these unknown parameters is considerably smaller than that of the direct filter design methods. Besides these unknown parameters, the proposed method needs some predefined multipliers. Although the number of these multipliers is larger than the number of unknown parameters, they are known a priori. The proposed method is generally applicable to any linear-phase FIR filter irrespective of its order being high, low, even, or odd as well as the impulse response being symmetric or antisymmetric. However, it is more efficient for filters with high orders as the conventional design of such filters is more challenging. For example, to design a linear-phase FIR lowpass filter of order 131071 with a stopband attenuation of about 55 dB, which is used as the prototype filter of a cosine modulated filter bank (CMFB) with 8192 channels, our proposed method requires only 16 unknown parameters. The paper gives design examples for individual lowpass filters as well as the prototype filters for fixed and flexible modulated FBs.

Industrial designers and educators who plan to design microelectronic systems (e.g. hardware accelerators, co-processors, etc.) are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic components such as field-programmable gate arrays (FPGAs) offered by Xilinx, Altera, Actel and others. This approach places the emphasis on high-level design which reduces time to market by relying on synthesis software and programmable logic to produce working prototypes rapidly. These prototypes may then be altered as requirements change or converted into high-volume mask gate arrays or other application-specific integrated circuits (ASICs) when the demand is known to be sufficient. These ASICs, however, must be designed to be testable to screen out those with manufacturing defects. Hence, scan logic must be inserted, test vectors generated and fault grading performed to ensure a high level of testability. These efforts complicate and delay the conversion of FPGA designs to ASICs but must be considered by designers of microelectronic systems. Topics covered include: design flow; system partitioning; hardware description languages (HDLs); specifying behavioral control; specifying structural components; critical paths; placement and routing; technology choices; FPGA applications; rapid prototyping; retargeting; manufacturing defects; scan chain insertion; test vector generation; fault grading, and ASIC production

In software defined radio (SDR) receivers, sample rate conversion (SRC) and channelization are two computational intensive tasks. Coefficient-less cascaded-integrator-comb (CIC) filters achieve SRC with low computational complexity, but the design of its gain droop compensation filter involves coefficients. These coefficients vary with the change in radio standards. In this paper, an architecture for variable digital filter (VDF) for gain droop compensation employing a set of fixed coefficient sub-filters and multi-dimensional polynomials in terms of spectral parameters is realized based on distributed arithmetic (DA). As the coefficients in the sub-filters are fixed, the proposed method uses ROM-based LUTs giving rise to low computational complexity. The proposed DA–VDF filter is synthesized on an application specific integrated circuit (ASIC) employing CMOS 90[Formula: see text]nm technology using Synopsis Design Complier. The proposed architecture achieves low latency at a reduced area delay product (ADP) of 78% and an efficiency of 72% in energy per sample (EPS) when compared with the conventional MAC-based architecture.

The ATLAS level-1 muon endcap trigger system is divided into three parts; one off-detector part and two on-detector parts. Application specific ICs (ASICs) and anti-fuse Field Programmable Gate Array (FPGAs) are actively used in the on-detector parts. A Low-Voltage Data Signaling (LVDS) serial link is used for the data transfer between the two on-detector parts (15 m apart) and G-Link (Hewlett-Packard 1.4 Gbaud high speed data link) with optical transmission (90 m) is used from one of the on-detector parts to the off-detector part. These components will be exposed to a radiation of approximately 200 Gy (including safety factors) for ten years corresponding to a total ionizing dose (TID) and a hadron fluence of 2/spl times/10/sup 10/ hadrons/cm/sup 2/. We have investigated systematically the radiation susceptibility to both the total ionizing dose and the single event effects for ASIC, FPGA, and Commercial Off The Shelf (COTS) serializer and deserializer chipsets for two types of LVDS serial link and one G-Link type. In this documentation we report the result of the irradiation tests for these devices and discuss their validity in the ATLAS system.

The effort in reducing the area of AES implementations has largely been focused on Application-Specific Integrated Circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naive implementation of the AES S-box has been the status-quo on Field-Programmable Gate Arrays (FPGAs). A similar discrepancy holds for masking schemes – a wellknown side-channel analysis countermeasure – which are commonly optimized to achieve minimal area in ASICs.In this paper we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction of the area footprint on FPGA devices. We present new AES implementations which improve on the state of the art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Guneysu at ASAP 2016. We further explore the protection of such implementations against first-order side-channel analysis attacks. Targeting the small area footprint on FPGAs, we introduce a heuristic-based algorithm to find a masking of a given function with d + 1 shares. Its application to our new construction of the AES S-box allows us to introduce the smallest masked AES implementation on Xilinx FPGAs, to-date.

Long-range low-power localization is a key technology that enables a host of new applications of wireless sensor nodes. We present RF-Echo, a new low-power RF localization solution that achieves decimeter accuracy in long range indoor non-line-of-sight (NLOS) scenarios. RF-Echo introduces a custom-designed active RF reflector ASIC (application specific integrated circuit) fabricated in a 180nm CMOS process which echoes a frequency-shifted orthogonal frequency division multiplexing (OFDM) signal originally generated from an anchor. The proposed technique is based on time-of-flight (ToF) estimation in the frequency domain that effectively eliminates inter-carrier and inter-symbol interference in multipath-rich indoor NLOS channels. RF-Echo uses a relatively narrow bandwidth of $\leq$80 MHz which does not require an expensive very high sampling rate analog-to-digital converter (ADC). Unlike ultra-wideband (UWB) systems, the active reflection scheme is designed to operate at a relatively low carrier frequency that can penetrate building walls and other blocking objects for challenging NLOS scenarios. Since the bandwidth at lower frequencies (2.4 GHz and sub-1 GHz) is severely limited, we propose novel signal processing algorithms as well as machine learning techniques to significantly enhance the localization resolution given the bandwidth constraint of the proposed system. The newly fabricated tag IC consumes 62.8 mW active power. The software defined radio (SDR) based anchor prototype is rapidly deployable without the need for accurate synchronization among anchors and tags. Field trials conducted in a university building confirm up to 85 m operation with decimeter accuracy for robust 2D localization.

Hardware acceleration using field programmable gate arrays (FPGAs) has become increasingly popular for computationally intensive digital signal processing (DSP) applications. Unfortunately, while FPGAs have a reasonably tractable computer aided design (CAD) flow and performance, they have poor power characteristics when compared to direct application specific integrated circuit (ASIC) fabrication. ASICs exhibit better performance and power than FPGAs, but require complex CAD and large non-recurring engineering (NRE) costs. A reconfigurable device that exhibits ASIC-like power characteristics and FPGA-like costs and tool support is desirable to fill this void. Several coarse-grained fabric architectures proposed during the last decade have been focused on performance and area-efficient architectural techniques. Even though power is becoming one of the critical design concerns for semiconductor industry, this issue has not been adequately addressed in the existing coarse-grained fabric architectures. In this paper, a low-power and high-performance hardware acceleration engine for DSP style applications is described. This reconfigurable fabric model is generic and parameterizable allowing design parameters to be adjusted within the architecture. The impact of varying different design parameters such as functional unit granularity, and multiplexer cardinality are studied for their implications on power and performance. The low-power fabric was designed to operate within the SuperCISC processor architecture designed at the University of Pittsburgh