Sampling Rate Conversion Techniques- A Review

New VLSI high throughput parallel structures for arbitrary rate non integer ratio sample rate conversion are presented in the paper. High throughput Sample Rate Converters (SRC) find application in high data rate Software Defined Radio (SDR) where a large degree of flexibility is required to support varied sample rates. Parallel Signal Processing implementations offer higher throughput for lower clock speeds. This makes them ideal for high data rate modem implementations on FPGA's or in power limited ASIC designs. The Farrow structure offers unique advantages ideal for parallel implementation. These unique qualities allow the utilization of novel reduced complexity parallel finite-length impulse response (FIR) filters. The structures presented in this paper are suitable for implementation on application specific integrated circuits (ASIC) or field programmable gate arrays (FPGA). Results shown here are for implementation on FPGAs with varying orders of parallelization.

ASoftware Defined Radio (SDR) system is a radio communication system, which uses software for modulation and demodulation of radio signals.In software defined radio (SDR) receivers, high-precision clock with very low jitter is required.It is intuitive to use only one fixed master clock.However, different wireless standards use different master clock rates.Under such circumstances, digital sample rate conversion (SRC) can be used as an important solution to provide different clock rates.The basic methods used in the SRC technology are decimation with down-sampling and interpolation with up-sampling, Down-sampling has to be preceded by filtering in order to avoid aliasing, while up-sampling must be followed by filtering to reject spectral images.In this paper, the design was implemented in FPGA using Verilog.The sampling rate conversion is performed by sampling the incoming signal and interpolating/decimating the signal to the desired value and then applying the low pass filter to eliminate aliasing.The sampling is done by digital mixer (Numerical controlled oscillator).The Interpolation/Decimation is performed by the CIC filter.FIR filter performs the low-pass filtering.The sampling rate converted value is given to the DSP processor for further processing.The projected application of the CSR_SDR are in GSM handset, CDMA handset and all the wireless applications.In this paper the functionality has been implemented, verified and checked using Verilog.

Digital filters with variable bandwidth can be used for a variety of applications. Arbitrary change in the bandwidth of a digital Finite Impulse Response (FIR) filter can be acquired using sampling rate converters. In this paper, a sampling rate converter is proposed which is generated from Pascal structure, a fractional delay filter having low hardware complexity and high modularity. The proposed sampling rate converter requires lesser number of multipliers for implementation when compared with the sampling rate converters in the literature. A low pass filter having a single bandwidth sandwiched between two sampling rate converters can contribute multiple bandwidths in such a way that each bandwidth is an arbitrary variation of the original bandwidth. A two stage Frequency response masking approach (FRM) is used for the hardware efficient design of the original low pass filter. A low complexity and high modularity novel design for a continuously varying bandwidth of a digital FIR filter is proposed in this paper using the proposed sampling rate converter. The modularity of the Pascal structure can be used to control both pass band ripple as well as stop band attenuation of the continuously variable bandwidth FIR filter design. Different communication standards in a Software defined radio (SDR) channelizer is realized using the proposed design of continuously variable bandwidth filter.

Adaptive sample rate converters (SRC) for the multi-standard mobile transceiver have been designed. GSM, UMTS and HIPERLAN2 standards have been chosen to establish the requirements for the SRCs. In the transmitter, the output signal of the data modulator is sampled at the symbol or chip frequency specified by the standards and needs to be converted into a common updating frequency of the D/A-converter. Pulse shaping and emission mask requirements are taken into account. In the receiver, A/D-conversion is also performed at a common fixed clock rate. Thus the SRC is needed to convert the A/D-converter sampling rate into a symbol or chip frequency that will be applied for further baseband signal processing. Channelization requirements defined by the standards are used as criteria for the performance analysis in the receiver. Based on the performance analysis, the complexity analysis is covered. It includes computational complexity, gate count, area and power consumption estimation for the chosen platform.

The ultimate objective of Software Defined Radio (SDR) is to replace the entire analog signal processing in the wireless transceivers with digital signal processing. This will provide the flexibility, through reconfiguration or reprogramming, to enable the transceivers to work with different air-interfaces standards using a single generic hardware platform. Most of the research in SDR to date has been focused on base stations, which do not have as tight constraints in size and power consumption as handsets. However, in order to realize the promise of integrated services and global roaming capabilities, the design and development of a multi-standard SDR handset with dynamic reconfigurability is crucial. The size and power constraints imposed by handsets with limited resources pose a major design challenge. This special issue brings together 11 papers that address various aspects of this challenge from the perspectives of wireless systems, computing architectures, embedded systems and signal processing. The most important part of an SDR transceiver is the wideband analog-to-digital converter (ADC) that converts the radio frequency signal received by the antenna into digital form for further processing. The first paper, “A multi-mode sigma-delta ADC for GSM/WCDMA/WLAN applications” by Jose et. al. proposed a cascaded reconfigurable sigma-delta modulator that is able to work with three different communication standards. This design, implemented in 0.18 μm CMOS technology, exhibits excellent signal-to-noise plus distortion ratios and has reduced power consumption compared to conventional designs. After ADC, the digitized received signal will need to be separated into signals within the various bands specified by the communication standard. This is performed by the channelizer which has the highest computational requirements of the whole SDR system. The second paper, by Panicker et al., reviews the state-of-the-art filter bank channelizer techniques with low power and dynamic reconfigurability properties. The design of reconfigurable devices can be optimized using the methodology of parametrization which bring together the common aspects of a myriad number of wireless standards into a single processing procedure. In this way, the implementation of the multi-standard SDR will be greatly simplified. “Promising technique of parametrisation for reconfigurable radio, the Common Operators Technique: fundamentals and examples” by Alaus et al. presents the common operator technique for parametrization which is less standards dependent than the more conventional Common Function technique. The direct digitization of the radio frequency (RF) signal requires very high speed ADCs which is not readily available using current technology. Therefore, current SDR implementations typically down-converts the RF A. P. Vinod (*) School of Computer Engineering, Nanyang Technological University, Nanyang, Singapore e-mail: asvinod@ntu.edu.sg

For extended mission utility, it is desirable to be able to reprogram on -orbit payloads for new functions not originally envisioned. The basic concept of modifying payloads in orbit is already proven in that software patches and new coding algorithms can be uploaded to payloads years after launch. The goal of this paper is to discuss the option to extend this reprogrammability to payload hardware, using standards and architectures proven in software -defined radio technology. Next generation payloads using these standards can exploit the increasing versatility and density o f modern Field Programmable Gate Arrays and Digital Signal Processing chips to perform new missions that require onboard wideband, real time processing. I. Introduction HIS paper discusses the application of proven software standards and design methodology to enable next generation multifunction payloads. Even though the physics of specific front -end sensors, emitters and associated electronics in the payload must conform to the original mission, the trend is moving toward increasing generalization and digi tal processing onboard, along with more generalized digital control of the front ends . New missions can take advantage of this trend by relying on generalized hardware that is programmed to be mission specific and reprogrammed as missions change . As onbo ard processing bandwidths increase over time, to tens and hundreds of Megahertz, these missions will benefit from the ever -increasing performance of digital technology in field -programmable gate arrays (FPGAs) to achieve their original and future objective s, increasing the payloads’ effectiveness while reducin g size, weight, power and cost. This approach also benefits operationally responsive satellite missions by reducing the serial development cycle, as a result of reusing common hardware and applying pro ven software to the task of on -orbit reconfiguration. Reconfiguring and reprogramming the FPGA -based payload in the field is similar to sending a new software load to an onboard microprocessor. However, the standards for uploading new functionality to a hardware target are not in such a mature form as for software, which use operating systems and monitor programs that can accommodate new program uploads . This paper specifically suggests the use of modern software -defined radio (SDR) standards to be appl ied more widely, to enable management and upgrading of generalized hardware -based, wideband payload functions. Figure 1 shows the generalized block diagram of a reconfigurable payload.

In the past, radio systems were designed to communicate using one or two wave forms. As a result, two groups of people with different types of traditional radio were not able to communicate due to incompatibility. The need to communicate with people using different types of equipment can only be solved by using software defined radio (SDR). SDR is a wireless device that works with any communication system, be it a cellular phone, a pager, a WI-FI transceiver an AM or FM radio, a satellite communications etc. In both hardware and software Digital Signal Processing (DSP) techniques are used to design a real time system. For SDR applications involving high complexity, it becomes impossible to stay with single sampling rate and so altering the sampling rate at different stages is required for low cost DSP hardware. Thus variable sampling rates i.e. Multirate Digital Signal Processing is required.

In software defined radio (SDR) receivers, sample rate conversion (SRC) and channelization are two computational intensive tasks. Coefficient-less cascaded-integrator-comb (CIC) filters achieve SRC with low computational complexity, but the design of its gain droop compensation filter involves coefficients. These coefficients vary with the change in radio standards. In this paper, an architecture for variable digital filter (VDF) for gain droop compensation employing a set of fixed coefficient sub-filters and multi-dimensional polynomials in terms of spectral parameters is realized based on distributed arithmetic (DA). As the coefficients in the sub-filters are fixed, the proposed method uses ROM-based LUTs giving rise to low computational complexity. The proposed DA–VDF filter is synthesized on an application specific integrated circuit (ASIC) employing CMOS 90[Formula: see text]nm technology using Synopsis Design Complier. The proposed architecture achieves low latency at a reduced area delay product (ADP) of 78% and an efficiency of 72% in energy per sample (EPS) when compared with the conventional MAC-based architecture.

This paper presents an approach of model-based design for implementing a digital communication system on a field programmable gate array (FPGA) for a software defined radio (SDR). SDR is a popular prototyping platform for wireless communication systems due to its flexibility and utility. A traditional SDR system performs nearly all computations and signal processing tasks on the host computer, and then sends the waveform to the RF front end. For complex algorithms or high data rate, the host computer becomes the processing bottleneck and FPGA is often employed as a hardware accelerator. This paper demonstrates the procedure of using model-based design for SDR targeted on FPGA hardware. A complete digital communication system, including a transmitter with convolutional encoder and a receiver with Viterbi decoder, is implemented on an FPGA-based SDR platform and validated by over-the-air demonstration. Synchronization algorithms, such as carrier frequency offset, phase offset, and time recovery, are also optimized for hardware efficiency.

New wireless communications standards do not replace old ones, instead the number of standards keeps on increasing and by now an abundance of standards exists. Moreover there is no reason to assume that this trend will ever stop. Therefore, the software-radio concept is emerging as a potential pragmatic solution: a software implementation of the user terminal able to dynamically adapt to the radio environment in which the terminal is located. For manufacturers this could result in shorter development time, cheaper production due to higher volumes. Furthermore software radio has advantages for consumers because it enables only software updates for new functionality without new hardware. Because of the analog nature of the air interface, a software radio will always have an analog front-end. In an ideal software radio, the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC) are positioned directly after the antenna. Such an implementation is not feasible due to the power that such a device would consume and other physical limitations. It is therefore a challenge to design a system that preserves most properties of the ideal software radio while being realizable with current-day technology. Such a system is called a software-defined radio (SDR). A flexible, all-standard radio will consume more energy than a dedicated radio for a single standard. The first flexible radio could be an application where power consumption is less an issue; an example being a flexible radio in a notebook. This thesis presents such a radio with the focus on wireless LAN standards. These standards use phase modulation or OFDM in the $2.4$ GHz or $5$ GHz frequency band, so we decided in our project to combine a receiver of a phase modulation standard (Bluetooth) with an OFDM receiver (HiperLAN/2) first. In our view SDR is an implementation technology: the HiperLAN/2 hardware is that complex to the Bluetooth hardware that the Bluetooth receiver may be added to the HiperLAN/2 one at limited costs. In this thesis we describe how the physical layer of the OSI model of a phase-modulation receiver can be combined with an OFDM receiver at a functional level. The second goal of this research is to investigate whether this combined receiver can be implemented in software running on a General Purpose Processor (GPP) and estimate the costs of such an implementation with respect to power consumption and computational power requirements. For this reason, a testbed has been developed where all baseband physical layer functions have been successfully mapped on a Pentium 4 processor. This has been tested in combination with a CMOS-integrated wideband analog SDR front-end, containing a low noise amplifier, down-conversion mixers and filters. The testbed can be extended to other standards, because the only limitations in our testbed are the maximal channel bandwidth of $20$ MHz, the dynamic range of the wideband SDR analog front-end and the processing capabilities of the used PC. In 1999, Bose showed for second-generation mobile standards that it is possible to perform most baseband functions of the physical layer on a GPP processor. In his research, I/O was one of the main bottlenecks. In thesis we have identified that this is no longer true for current-day computers. Nowadays, an important bottleneck is the latency of the operating system, because wireless standards require fast response times. Major contributions of this thesis to the field of SDR research are extending the work of Bose for wireless LAN standards and developing a functional SDR receiver architecture that is capable of receiving standards that use OFDM or phase modulation.

Software-defined radio (SDR) is an emerging technology that offers various advantages over conventional radio designs. The SDR approach uses a common hardware platform, programmed by software modules and firmware, to support many communications standards and operating frequencies. The technology is being promoted by the US Department of Defense to replace tens of thousands of single-protocol, single-purpose radios with a common platform. Military and public safety organisations worldwide are also considering this technology to solve interoperability problems enabling, for example, police and firefighters to easily communicate in the field. In addition, the commercial wireless industry views SDR as a means of reducing development cost and time to market. To fully realize SDR’s promise of an all-encompassing communications device capable of transmitting and receiving over a very wide frequency range requires special attention to the radio frequency (RF) transceiver. Although it is relatively easy to use conventional electronics to build SDRs operating at up to 6GHz, it is increasingly difficult to do so at higher operating frequencies. It needs a hardware platform capable of operating up to about 60GHz to take full advantage of the SDR concept. Ideally, the SDR hardware platform has a continuouslytunable source to act as a local oscillator. It should be possible to modulate this source in any format, perform signal conditioning, and distribute the signal: either by wireless transmission or over an optical network. The prospect of using conventional electronics to develop a commercially-viable source with these properties is limited, so it may be necessary to find another approach. Optical technology can emulate many of the functions normally associated with RF reception and transmission. For example, it is possible to generate microwave signals optically over a very large frequency range—from MHz to THz—using heterodyne techniques such as optical injection locking, optical phaselocked loops, and nonlinear up-conversion. The electrical RF signal is generated by shining two optical inputs, separated by the desired microwave frequency, on to a square-law photodetector that acts as a mixer and generates their beat frequency. In general, when no phase or frequency control is applied, the phase noise of the microwave signal is approximately equal to the sum of the optical linewidths. The key to reducing this typicallyMHz linewidth down to values that are more practical for a communications system is to ensure that the phases of the optical signals are highly correlated. If they are, a very narrow RF linewidth can be achieved, even from large-linewidth optical sources. A carrier is of limited use in a communication system without some form of encoded information. A laser source can be modulated by inserting a baseband optical modulator in the optical path, or by other means. The modulation formats are varied and may act on the frequency, amplitude, or phase of the signal. In general, the bandwidth of the modulator/demodulator is dictated by the format of the protocol or the radio-spectrum channel allocation and is relatively modest, since the high-frequency carrier is already optically generated. This means that digital demodulation can be done directly by the computer, after optical down-conversion, to make it easier to interface with the SDR software. Both the receiver and transmitter need RF filtering for signal conditioning. Techniques for electrical filtering in the optical domain have been examined extensively, but the all-optical microwave filters proposed to date are primarily based on incoherent manipulation of optical carriers with only positive taps. This approach can only create low-pass filters. Many applications, including SDR systems, need bandpass and flat-top filters as well. To overcome this limitation, Yao et. al. recently reported a way to build an all-optical microwave bandpass filter with a simple structure.

It is expected that multiple radio access standards and systems will coexist in the same environment beyond 3G. The superior re-configurability and re-programmability of software-defined radio (SDR) had made itself become the most promising technology to realize such a flexible radio system. Several research projects have involved in the development of SDR systems, but their efforts mainly focus on hardware design. A software framework that allows users, manufactures or operators to insert, remove, update and configure protocols, applications and hardware modules is also an essential part of a SDR system. Unfortunately, current commercial operating systems (OS) lack of fully supports of SDR features. In this paper, the impacts of SDR on the OS and the extension of the OS for a SDR system are investigated. Moreover, the design and implementation of a software framework based on a commercial on-the-shelf (COTS) OS are also presented.

Software Defined Radios (SDRs) are wireless communication systems in which many of the radios' important functional elements, including filtering, frequency translation and modulation/demodulation, are implemented in software via Digital Signal Processing (DSP) techniques using embedded processors and Field Programmable Gate Arrays (FPGA) as described by Harris and Lowdermilk in 2010 [1]. SDRs differ from traditional radios that typically employ custom silicon to implement such functions. SDRs exhibit several advantages over traditional radios, including re-configurability and reduced development costs and time-to-market since they do not require custom silicon. SDRs also enjoy long life cycles, since they can readily be adapted to meet future needs. Cognitive Radios (CRs) are a special class of SDRs that employ adaptive DSP technologies to implement spectral management. This enables CRs to deliver improved effective bandwidth, quality of service, and enhanced security, which have become increasingly important in modern commercial and military wireless communications applications.

The role of filtering in sampling-rate conversion has been considered in Chapter II. The importance of filtering arises from the fact that the sampling theorem should be respected for all the sampling rates of the system at hand. Filters are required to bandlimit the spectrum of the signal to the prescribed bandwidth in accordance with the actual sampling rate. In sampling rate conversion systems, filters are used in decimation to suppress aliasing and in interpolation to remove imaging. Since an ideal frequency response cannot be achieved, the performance of the system for sampling rate conversion is mainly determined by filter characteristics. Obviously, an appropriate filter should enable the sampling rate conversion with minimal signal distortion. The main advantage of a multirate system is the computational efficiency, and therefore, a decimator (interpolator) that implements a high-order digital filter could not be tolerated. The specific role of a digital filter in sampling rate conversion demands high-performance filtering with the lowest possible complexity. To reach this goal one has to concentrate first on the choice of the appropriate design specifications in order to provide minimal signal distortion. Secondly, the multirate filter is to be designed in a manner to satisfy the prescribed characteristics and to provide a low-complexity implementation structure. In this chapter, we discus first the spectral characteristics of decimators and interpolators and introduce three commonly used types of filter specifications. In the sequel, we review the MATLAB functions that are appropriate for the design of FIR and IIR filters to satisfy the specifications. An approach to computation of aliasing characteristics of decimators is given and illustrated by examples. This chapter considers also the analysis of sampling rate conversion for band-pass signals. Chapter concludes with MATLAB exercises for individual study.

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.