Performance and complexity analysis for adaptive sample rate converters in GSM/UMTS/HIPERLAN2 mobile transceiver

In the recent few years, it is observed that in wireless communication there has been a rapid growth in terms of different communication standards/ technologies being used. Thus, to support different communication standards, flexible system should be used to convert the digital signal from one sample rate to another (up sampling or down sampling). The solution is the use of Software defined Radio (SDR), which is a reconfigurable radio communication system. Therefore the most critical and demanding element in the digital signal processing chain of an SDR is the Sample Rate Converter. At high sampling rate, the signals cannot be processed by using baseband signal processing unit. Instead of any unique air-interface, SDR simultaneously handles multiple air-interfaces of different wireless standards that require sample rates for baseband processing. Thus, in SDR, Sampling Rate Conversion (SRC) is an important functionality to provide synchronization between the ADC and baseband signal processor. This paper provides a review on various types of SRC circuits, where their design characteristics are analyzed and compared. The review is based on designing of Sample Rate converters on Field-Programmable Gate Array (FPGA) and Applications Specific Integrated Circuit (ASIC) platform. For FPGA based design, LUT, slices, FFT, and other hardware resource parameters are estimated to evaluate their performance. For ASIC, area, power and delay are considered for performance evaluation.

The role of filtering in sampling-rate conversion has been considered in Chapter II. The importance of filtering arises from the fact that the sampling theorem should be respected for all the sampling rates of the system at hand. Filters are required to bandlimit the spectrum of the signal to the prescribed bandwidth in accordance with the actual sampling rate. In sampling rate conversion systems, filters are used in decimation to suppress aliasing and in interpolation to remove imaging. Since an ideal frequency response cannot be achieved, the performance of the system for sampling rate conversion is mainly determined by filter characteristics. Obviously, an appropriate filter should enable the sampling rate conversion with minimal signal distortion. The main advantage of a multirate system is the computational efficiency, and therefore, a decimator (interpolator) that implements a high-order digital filter could not be tolerated. The specific role of a digital filter in sampling rate conversion demands high-performance filtering with the lowest possible complexity. To reach this goal one has to concentrate first on the choice of the appropriate design specifications in order to provide minimal signal distortion. Secondly, the multirate filter is to be designed in a manner to satisfy the prescribed characteristics and to provide a low-complexity implementation structure. In this chapter, we discus first the spectral characteristics of decimators and interpolators and introduce three commonly used types of filter specifications. In the sequel, we review the MATLAB functions that are appropriate for the design of FIR and IIR filters to satisfy the specifications. An approach to computation of aliasing characteristics of decimators is given and illustrated by examples. This chapter considers also the analysis of sampling rate conversion for band-pass signals. Chapter concludes with MATLAB exercises for individual study.

The wideband signal is sampled at a high rate in digital IF(intermediate frequencies) receiver using a fixed master clock. After extracting individual narrowband channels from wideband signal, the sample rate is much higher than single channel bandwidth. It is necessary to resample the signal with a lower rate to reduce data redundancy. And the receiver should has the capability of operating in all sorts of communication standard. So sensitive SRC(sample rate conversion) is necessary in the receiver. The paper proposed an efficient SRC architecture and an optimized algorithm for assigning changing rate factor. The architecture is programmable, hardware sharing, with lower power consumption, which take advantage of renewed comb filters to improve alias rejection and reduce power consumption of the decimation at high rate. The optimized algorithm is flexible and simple. It can realize SRC efficiently by optimum composition of algorithmand architecture.

Digital filters with variable bandwidth can be used for a variety of applications. Arbitrary change in the bandwidth of a digital Finite Impulse Response (FIR) filter can be acquired using sampling rate converters. In this paper, a sampling rate converter is proposed which is generated from Pascal structure, a fractional delay filter having low hardware complexity and high modularity. The proposed sampling rate converter requires lesser number of multipliers for implementation when compared with the sampling rate converters in the literature. A low pass filter having a single bandwidth sandwiched between two sampling rate converters can contribute multiple bandwidths in such a way that each bandwidth is an arbitrary variation of the original bandwidth. A two stage Frequency response masking approach (FRM) is used for the hardware efficient design of the original low pass filter. A low complexity and high modularity novel design for a continuously varying bandwidth of a digital FIR filter is proposed in this paper using the proposed sampling rate converter. The modularity of the Pascal structure can be used to control both pass band ripple as well as stop band attenuation of the continuously variable bandwidth FIR filter design. Different communication standards in a Software defined radio (SDR) channelizer is realized using the proposed design of continuously variable bandwidth filter.

This paper introduces multimode transmultiplexers (TMUXs) in which the Farrow structure realizes the polyphase components of general lowpass interpolation/decimation filters. As various lowpass filters are obtained by one set of common Farrow subfilters, only one offline filter design enables us to cover different integer sampling rate conversion (SRC) ratios. A model of general rational SRC is also constructed where the same fixed subfilters perform rational SRC. These two SRC schemes are then used to construct multimode TMUXs. Efficient implementation structures are introduced and different filter design techniques such as minimax and least-squares (LS) are discussed. By means of simulation results, it is shown that the performance of the transmultiplexer (TMUX) depends on the ripples of the filters. With the error vector magnitude (EVM) as the performance metric, the LS method has a superiority over the minimax approach.

In Generalized Frequency Division Multiplexing (GFDM) underwater acoustic communication systems, the conventional Doppler shift factor estimation will reduce the transmission rate of the system. The sampling rate conversion of the received signal usually adopts the resampling method, thereby increasing the computational complexity. Aiming at the above problems, a Doppler shift factor (DFS) estimation algorithm based on oversampling technique and a sampling rate conversion algorithm is proposed. The Doppler shift factor is estimated by comparing the transmitted signal with the received signal samples. On this basis, the above-sampled data and a linear interpolation algorithm are used to convert the sampling rate of the received signal. The theoretical analysis and simulation results show that the improved algorithm can greatly reduce the computational complexity of the receiver while ensuring the performance of the system and is suitable for high-speed real-time underwater acoustic communication systems.

ASoftware Defined Radio (SDR) system is a radio communication system, which uses software for modulation and demodulation of radio signals.In software defined radio (SDR) receivers, high-precision clock with very low jitter is required.It is intuitive to use only one fixed master clock.However, different wireless standards use different master clock rates.Under such circumstances, digital sample rate conversion (SRC) can be used as an important solution to provide different clock rates.The basic methods used in the SRC technology are decimation with down-sampling and interpolation with up-sampling, Down-sampling has to be preceded by filtering in order to avoid aliasing, while up-sampling must be followed by filtering to reject spectral images.In this paper, the design was implemented in FPGA using Verilog.The sampling rate conversion is performed by sampling the incoming signal and interpolating/decimating the signal to the desired value and then applying the low pass filter to eliminate aliasing.The sampling is done by digital mixer (Numerical controlled oscillator).The Interpolation/Decimation is performed by the CIC filter.FIR filter performs the low-pass filtering.The sampling rate converted value is given to the DSP processor for further processing.The projected application of the CSR_SDR are in GSM handset, CDMA handset and all the wireless applications.In this paper the functionality has been implemented, verified and checked using Verilog.

Data receivers for storage systems normally operate at a fixed sampling rate 1/T s that is asynchronous to the baud rate 1/T. A sampling-rate converter (SRC) serves to convert the incoming signal from the asynchronous to the synchronous clock domain. These receivers also contain an equalizer that serves to suppress intersymbol interference and noise. To limit receiver complexity, equalization burden can be shifted towards the SRC. This possibility is not exploited in any existing SRC. This paper presents SRC design methods that combine group delay flatness and out-of-band rejection criteria with the minimum mean square error equalization criterion. Numerical examples for an idealized optical recording channel validate the design methods.

Spectral analysis is a widely used method to estimate 1/fα noise in behavioral and physiological data series. The aim of this paper is to achieve a more solid appreciation for the effects of periodic sampling on the outcomes of spectral analysis. It is shown that spectral analysis is biased by the choice of sample rate because denser sampling comes with lower amplitude fluctuations at the highest frequencies. Here we introduce an analytical strategy that compensates for this effect by focusing on a fixed amount, rather than a fixed percentage of the lowest frequencies in a power spectrum. Using this strategy, estimates of the degree of 1/fα noise become robust against sample rate conversion and more sensitive overall. Altogether, the present contribution may shed new light on known discrepancies in the psychological literature on 1/fα noise, and may provide a means to achieve a more solid framework for 1/fα noise in continuous processes.

New VLSI high throughput parallel structures for arbitrary rate non integer ratio sample rate conversion are presented in the paper. High throughput Sample Rate Converters (SRC) find application in high data rate Software Defined Radio (SDR) where a large degree of flexibility is required to support varied sample rates. Parallel Signal Processing implementations offer higher throughput for lower clock speeds. This makes them ideal for high data rate modem implementations on FPGA's or in power limited ASIC designs. The Farrow structure offers unique advantages ideal for parallel implementation. These unique qualities allow the utilization of novel reduced complexity parallel finite-length impulse response (FIR) filters. The structures presented in this paper are suitable for implementation on application specific integrated circuits (ASIC) or field programmable gate arrays (FPGA). Results shown here are for implementation on FPGAs with varying orders of parallelization.

Lattices sampling and sampling rate conversion of multidimensional bandlimited signals in the linear canonical transform domain

The concept of multirate signal processing is playing an increasingly important role in the areas of wireless communication and networking. Decimation and interpolation are the very effective and popular computation methods adopted in sampling rate conversion(SRC). In this paper, sampling rate conversion for Digital Audio Tape (DAT) to Compact Disc (CD) is discussed and implemented using multiple cascaded stages of Type-II Linear phase Multirate FIR filter. The symmetry property of FIR filter is exploited for reducing the computational complexity. The multiplication complexity is reduced for the proposed cascaded structure when compared to the conventional polyphase structure. Simulations have been done using MATLAB and simulink model has been developed to compare the performance of the proposed structure with the conventional polyphase FIR filter. The verilog code is generated using HDL coder. Analysis and synthesis is perfomed using Modelsim and Xilinx and the results are compared in terms of area and delay. The results shows that the propsed approach requires less area and delay.

This book is Volume III of the series DSP for MATLAB™ and LabVIEW™. Volume III covers digital filter design, including the specific topics of FIR design via windowed-ideal-lowpass filter, FIR highpass, bandpass, and bandstop filter design from windowed-ideal lowpass filters, FIR design using the transition-band-optimized Frequency Sampling technique (implemented by Inverse-DFT or Cosine/Sine Summation Formulas), design of equiripple FIRs of all standard types including Hilbert Transformers and Differentiators via the Remez Exchange Algorithm, design of Butterworth, Chebyshev (Types I and II), and Elliptic analog prototype lowpass filters, conversion of analog lowpass prototype filters to highpass, bandpass, and bandstop filters, and conversion of analog filters to digital filters using the Impulse Invariance and Bilinear Transform techniques. Certain filter topologies specific to FIRs are also discussed, as are two simple FIR types, the Comb and Moving Average filters. The entire series consists of four volumes that collectively cover basic digital signal processing in a practical and accessible manner, but which nonetheless include all essential foundation mathematics. As the series title implies, the scripts (of which there are more than 200) described in the text and supplied in code form here will run on both MATLAB™ and LabVIEW™. The text for all volumes contains many examples, and many useful computational scripts, augmented by demonstration scripts and LabVIEW™ Virtual Instruments (VIs) that can be run to illustrate various signal processing concepts graphically on the user's computer screen. Volume I consists of four chapters that collectively set forth a brief overview of the field of digital signal processing, useful signals and concepts (including convolution, recursion, difference equations, LTI systems, etc), conversion from the continuous to discrete domain and back (i.e., analog-to-digital and digital-to-analog conversion), aliasing, the Nyquist rate, normalized frequency, sample rate conversion and Mu-law compression, and signal processing principles including correlation, the correlation sequence, the Real DFT, correlation by convolution, matched filtering, simple FIR filters, and simple IIR filters. Chapter four of Volume I, in particular, provides an intuitive or first principle understanding of how digital filtering and frequency transforms work. Volume II provides detailed coverage of discrete frequency transforms, including a brief overview of common frequency transforms, both discrete and continuous, followed by detailed treatments of the Discrete Time Fourier Transform (DTFT), the z-Transform (including definition and properties, the inverse z-transform, frequency response via z-transform, and alternate filter realization topologies including Direct Form, Direct Form Transposed, Cascade Form, Parallel Form, and Lattice Form), and the Discrete Fourier Transform (DFT) (including Discrete Fourier Series, the DFT-IDFT pair, DFT of common signals, bin width, sampling duration, and sample rate, the FFT, the Goertzel Algorithm, Linear, Periodic, and Circular convolution, DFT Leakage, and computation of the Inverse DFT). Volume IV, the culmination of the series, is an introductory treatment of LMS Adaptive Filtering and applications, and covers cost functions, performance surfaces, coefficient perturbation to estimate the gradient, the LMS algorithm, response of the LMS algorithm to narrow-band signals, and various topologies such as ANC (Active Noise Cancelling) or system modeling, Periodic Signal Removal/Prediction/Adaptive Line Enhancement (ALE), Interference Cancellation, Echo Cancellation (with single- and dual-H topologies), and Inverse Filtering/Deconvolution/Equalization. Table of Contents: Principles of FIR Design / FIR Design Techniques / Classical IIR Design

In Digital audio processing, there are multiple standard sampling rates, for example, 48kHz for studio work, 44.1kHz for compact disk(CD) mastering. Therefore, sampling rate conversion is needed to interchange signals from one field to another. A rational sampling rate conversion by L/M can be done cascading an L-fold up-sampler and an M-fold down-sampler with a linear phase FIR lowpass filter in the middle. When both L and M have large values, the lowpass filters are required to have an extremely narrow normalized bandwidth and a sharp transition characteristic, causing difficulty in design and implementation. This paper describes a technique to overcome this difficulty for the case both L and M are composite numbers, giving an multistage converter structure where each stage is consisting of an up-sampler and a down-sampler, both of a small conversion ratios, with a filter having not so sharp normalized transition characteristic in the middle, remarkably reduced total computation complexity.

In this paper we describe design options when implementing sampling rate converters with FPGAs. We first review typical designs using IIR and FFT-based systems and then show implementations of fractional sampling rate changer ranging from Lagrange, B-spline to recently introduced C-MOMS and O-MOMS designs. Speed, area and error performance results for the circuits designed in VHDL are provided.