High-voltage accumulation-layer UMOSFET's in 4H-SiC

A low specific on-resistance (RS,on) silicon-on-insulator (SOI) trench MOSFET (metal—oxide—semiconductor—field—effect—transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced RS,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal—oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ·cm2 to 36.6 mΩ·cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.

High voltage MOSFETs are widely used for bias ranges of a few dozens of volts to a few hundred of volts. The trench-type MOSFET is one of the key devices for realizing this wide range applications. However, the device characteristics are not yet well understood, especially, the Miller-capacitance variation for different device structures is still mysterious. Here we show, that the capacitance variation is very much dependent on the applied device structure. An observed capacitance increase as a function of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> , contrary to the conventional decreasing trend, is due to the large induced field within the highly resistive drift region. A narrow width of the drift region in a super-junction structure will easily become fully depleted, due to the junction between drift and pillar region of the substrate, which causes a fully depleted condition. This full-depletion situation induces a high field within the drift region, resulting in a potential increase even at the gate oxide.

A RESURF-enhanced high voltage SOI LDMOS (ER-LDMOS) with an ultralow specific on-resistance (Ron, sp) is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer (BPL) under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension (JTE), but also forms a vertical reduced surface field (RESURF) structure with the N-drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer (BOX) exhibits a triple-RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage (BV) and a low Ron, sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron, sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron, sp by 91% compared with the conventional trench LDMOS at the same cell pitch.

A novel silicon-on-insulator (SOI) high figure-of-merit vertical double diffused MOSFET (VDMOS) structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). The accumulation charges located in the trenches enhance the electric field in the buried oxide layer and uniform the electric field in the drift region, therefore the breakdown voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</inf> ) is enhanced. Simulation shows that the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</inf> and the figure-of-merit of the TPSOI VDMOS increase by 66.8% and 148.1% in comparison with the conventional VDMOS, respectively.

The major challenge the radio frequency laterally double-diffused metal oxide semiconductor (RF LDMOS) faces today is the linearity and switching delay. In this paper, we propose a new, gate-engineered silicon-on-insulator (SOI) LDMOS device to overcome this problem. The proposed device has three gates arranged in a stepped manner, from the channel to drift region. The first gate uses p+ poly (near the source), whereas the other two gates have n+ poly. The first gate with a thin gate oxide achieves good control over the channel charge. The third gate with a thick gate oxide at the drift region achieves reduced gate to drain capacitance. The arrangement of second and third gates in a stepped manner in the drift region spreads the electric field uniformly. Using two-dimensional device simulations, the proposed LDMOS is compared with the conventional LDMOS. We demonstrate that the proposed device exhibits significant enhancements in linearity, switching delay, breakdown voltage, on-resistance, peak transconductance and gate-drain charge making it highly suitable for RF power amplifiers.

Two-dimensional numerical simulation studies of collector-emitter breakdown voltage (BV/sub CEO/) of a novel collector-tub lateral bipolar transistor (CTLBT) on silicon-on-insulator (SOI) are presented. The collector-tub is realized by etching the buried oxide (BOX) at the collector high-low (NN/sup +/) junction side followed by an N-implantation in a conventional lateral bipolar transistor (LBT) on SOI. Such a modification makes the collector potential to be absorbed both by the collector drift and substrate regions and the electric field spreads along the collector drift length. The simulation results show that by choosing appropriate buried oxide (BOX) thickness (t/sub OX/), collector-tub junction depth (X/sub j/), drift region doping (N/sub D/) and substrate doping (N/sub S/), the electric field profile in the collector drift region of the CTLBT can be redistributed so that its BV/sub CEO/ value is more than double when compared with a conventional lateral bipolar transistor on SOI. The reasons for this significant improvement in breakdown performance are explained.

In this paper, a new structure of SiC-base trench-gate MOSFET protected by vertical field plate is proposed. Compared with conventional trench gate MOSFET, a deep trench connected to the source is added. The source trench is filled with polysilicon and acts as a vertical field plate. Under blocking state, the depletion charge between trenches is coupled with the vertical field plate, which can modify the electric field distribution near the gate oxide corner. Lower field strength in gate-oxide is the guarantee for long-term reliable operation of the device. In order to investigate the effect of charge-coupling, double doped epitaxial drift region is selected. The doping concentration of first epi-layer is lower than that of second eip-layer. The bottom of the deep source trench, that is, the end of vertical field plate, falls at the junction for the two epitaxial layer. The static characteristics are simulated for both conventional trench gate and dual trench dual epitaxy new structures by using Sentaurus TCAD. Simulation results show that the new structure with double trenches and double epitaxy has higher Baliga's figures of merit (FOM) Also, under the blocking state, the maximum electric field in gate oxide can be lower than 5MV/cm. That is desirable for the long-term operation reliability of the gate.

A novel SOI trench LDMOS with vertical double-RESURF is studied in this paper. A p-type silicon pillar is inserted beside the oxide trench as a vertical double RESURF layer, which can effectively modulate the electronic field and enhance the doping concentration in the drift region. The drain n+ region extends to the surface of buried oxide layer, shortening the motion-path in the high-resistance n− drift region for the carriers. A significantly optimized dependence of specific on-resistance on breakdown voltage is obtained.

A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region. Gate oxide and silicon layer form the EG Structure-Oxide-Semiconductor structure that is similar to Metal–Insulator–Semiconductor capacitor. The the N-drift of the EG structure can obtain the charge compensation to overcome the SAD effect, and a nearly rectangular electric field is achieved. In the on-state, the EG structure has two conductive channels and the accumulation layer is formed on the drift region. By accumulating high concentration electrons in the channels, the specific on-resistance (RON,sp) is greatly reduced. When the drift length is 24 μm, 431.4 V breakdown voltage (VB) and 9.8 mΩ cm2 RON,sp are achieved, and the figure of merit is 18.9 MW cm−2.

Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm/sup 2//Vs for the NMOS devices and around 7.5 cm/sup 2//Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300/spl deg/C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300/spl deg/C.

As the performance of GaN- and SiC-based power devices becomes limited by fundamental material properties, semiconductors with larger bandgaps are appealing due to their superior material properties. Most notable is that the critical electrical field scales as the bandgap to the 2.0-2.5 power. Thus, diodes employing wide bandgap semiconductors are expected to operate at higher breakdown voltages with thinner and more heavily-doped drift regions, leading to lower resistive losses. AlGaN alloys with their much larger bandgap compared to SiC and GaN are thus appealing for high voltage pn diodes and transistors. Additionally, the formation of AlGaN-based heterojunctions and the utilization of polarization fields offer design options not possible for devices based on materials such as SiC and diamond. Here we report on the growth and performance of pn diodes fabricated from Al0.30Ga0.70N (Eg=4.1eV) and Al0.74Ga0.26N (Eg=5.3eV) alloys, illustrating the potential for AlGaN alloys as a viable material for next-generation power diodes. Quasi-vertical pn diodes consisting of Al0.30Ga0.70N epilayers were grown by metalorganic vapor phase epitaxy on 1.3 mm thick sapphire substrates. The added stiffness of such thick sapphire substrates (3x thicker than typical sapphire) reduces wafer bow and eliminates cracking in epitaxial structures up to 19 μm thick. Thick epitaxial structures are needed to achieve the > 4 microns thick drift layers necessary for multi-kilovolt breakdown voltages. A series of pn diode structures were grown where the thickness of the lightly doped drift layer (No = 2-5x1016 cm-3) was varied from 4.3 to 11 μm. All structures were completed with a 0.35 μm thick Mg-doped Al0.30Ga0.70N p-layer followed by a compositional grade to a p-GaN contact layer. Diodes employed a junction edge termination structure around the p-contact to reduce the peak electric field at the contact metal to avoid premature breakdown. Breakdown voltages from 1600 to 3000V were achieved in reverse bias and a forward turn-on voltage of 6 to 8 volts was recorded. To our knowledge, this is the first vertical AlGaN-based pn diode exhibiting a breakdown voltage in excess of 1 kilovolt. The differential specific on-resistance was higher than expected based on consideration of the drift region only (typically 16-20 mΩ-cm2), which is tentatively attributed to the resistance due to lateral current spreading in these front-contacted, quasi-vertical diodes. An effective critical electric field of 5.9 MV/cm was determined from the reverse current-voltage characteristics based on a punch-through, as dictated by the doping and thickness of the drift region. We have also investigated quasi-vertical pn diodes consisting of Al0.74Ga0.26N epilayers to exploit the expected higher critical electric field in higher aluminum mole fraction alloys. These diodes consisted of 4.5 μm thick AlN epilayers grown on sapphire followed by a heavily doped n-type contact layer. Next a lightly doped (No = 2-4x1016 cm-3) 5 or 8 μm thick drift layer was grown. The combination of a thick AlN buffer and Al0.74Ga0.26N layers resulted in x-ray diffraction linewidths of 164-197 (237–284) arc seconds for the (0002) and (10-12) reflections for the drift layer, respectively. By optimizing the growth conditions used for the drift layer, the density of electron compensating defects can be reduced to ~ 1x1016 cm-3 — a level reported for GaN pn diodes. Unlike GaN diodes where drift layer doping at mid to low 1015 cm-3 is necessary for breakdown voltages of several kilovolts, the free electron concentration in these Al0.74Ga0.26N pn diodes is significantly higher than the level of compensation, making doping much easier to control and illustrating the benefit of higher critical electric field. The drift layer was followed by p-type AlGaN and finally a compositional grade to a p-GaN contact layer. It is the p-AlGaN layer that is a significant challenge in Al-rich pn diodes. Unlike pn diodes based on Al0.30Ga0.70N epilayers, simple homojunction pn diodes are not practical in Al-rich AlGaN alloys due to the low hole concentration owing to the very deep (Ea > 400 meV) acceptor level. Consequently, other approaches must be considered for hole transport to the pn junction. We will report on the current-voltage characteristics of pn heterojunction diodes where a Mg-doped p-type Al0.30Ga0.70N layer is grown on the n-type Al0.74Ga0.26N drift layer. Additionally, the current-voltage characteristics of pn diodes where holes are generated in the p-region by field ionization of Mg acceptors will also be presented. Finally, practical pn diodes require specific on-resistance lower than what is inherent for front-contacted quasi-vertical device architectures grown on insulating substrates. We will report an approach that has realized vertically conducting AlGaN pn diodes employing AlGaN overgrowth on conducting GaN substrates.

A NUMBER of MOS developments have been attempted to provide operation at voltages higher than 200V1-?. Among these, DSA6 MOST seem to have a promising future. This paper will describe a high voltage, DSA MOS IC which operates in excess of 400V. It was designed as a driver for electroluminescent displays . Low voltage logic and thirty-two high-voltage output transistors are integrated on a single chip. The device consists of a pair of layers patterned as concentric conductive annular strips above which a layer of metal with a circular gap is deposited. This configuration and final passivation over the metal layer permit encapsulation in a plastic package. The high voltage DSA MOST was proposed earlier with a 71 substrate, a Diffusion-Self-Aligned structure, lightly doped drift region(N-), and a field plate extended from the draine lectrode? The drift region of this device was not covered by field plates; i.e., an offset gate structure. If the field plate is extended to cover all of?the drift region in these devices, the electric field at the edge of the drift region will be enhanced and the breakdown voltage reduced.

This paper introduces a new SiGe Stepped Gate (SSG) thin film SOI LDMOS for enhanced performance. The proposed device eliminates the premature breakdown of the device due to floating body effects, which is one major problem of the thin film SOI LDMOS. The most common technique used to eliminate the floating body effects in SOI power device is the source tied body contact. Though this technique is successful in thick film devices, its effectiveness to thin film LDMOS is questionable, and also it imposes area penalty. Without a body contact, the floating body effects can be also reduced by decreasing the drift region doping [1]. But increased drift region resistance degrades the on-resistance of the device. The proposed device, SSG LDMOS circumvents the above challenges. It has a germanium implanted source and stepped field plate in the drift region. The SSG LDMOS reduces floating body effects in two ways. The SiGe source offers low potential to the excess holes generated due to the impact ionization [2]. The stepped gate reduces gate-drain capacitance improving the switching speed. The combined effect of (i) SiGe in the source and (ii) the stepped gate, improves the breakdown voltage and also allows us to increase the drift doping levels resulting in a reduced on-resistance. Using two dimensional device simulation [3], the proposed device is simulated and compared with the conventional thin film LDMOS. The cross-sectional view of both the devices is shown in Fig. 1. The conventional LDMOS has a uniform gate oxide thickness of 50 nm with a field plate. The drift region doping in both the devices is chosen for maximum breakdown voltage and is found to be 9×10 16 cm -3 (which is higher than the conventional device doping 3×10 16 cm -3 ). The germanium mole fraction in the SiGe source of the SSG LDMOS is chosen to be 0.2. The device parameters used in our simulation are given in Table 1. Figs. 2 and 3 show the breakdown characteristics and the on-resistance variation of the SSG LDMOS and the conventional LDMOS. The SSG LDMOS exhibits a 97% improvement in breakdown voltage and a 61% reduction in onresistance compared to the convetional LDMOS. Figs. 4 and 5 show the switching delay and the gate-charge behaviour. We observe that the SSG LDMOS exhibits a 57% reduction in switching delay and a 50% reduction in gate-drain charge compared to the conventional LDMOS. This work clearly demonstrates the application of SiGe source and a stepped oxide gate in improving the performance of the LDMOS making this device more useful in both RF and wireless system-onchip applications.

A novel high-voltage light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) with buried p-layer (BP) is proposed in this paper. Since the negative charges in the BP layer modulate the bulk electric field distribution, the electric field peaks both at the junction of the p base/n-type carrier stored (N-CS) layer and the corners of the trench gates are reduced, and new electric field peaks appear at the junction of the BP layer/N− drift region. As a result, the overall electric field in the N− drift region is enhanced and the proposed structure improves the breakdown voltage (BV) significantly compared with the LPT CSTBT. Furthermore, the proposed structure breaks the limitation of the doping concentration of the N—CS layer (NN—CS) to the BV, and hence a higher NN—CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop (Vce(sat)) can be obtained with almost constant BV. The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm−3, a thickness of LBP = 2.5 μm, and a width of WBP = 5 μm, the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V, with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3. However, with the same N−-drift region thickness of 150 μm and NN—CS, the BV of the CSTBT decreases from 1598 V to 247 V. Meanwhile, the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3.